公开(公告)号：US20160380753A1

公开(公告)日：2016-12-29

申请号：US15262859

申请日：2016-09-12

Applicant: Intel Corporation

Inventor： Pankaj Vinayak Dudulwar ,  Chenchu Punnarao Bandi ,  Lip Khoon Teh ,  Tat Hin Tan

IPC: H04L7/00 ,  G11C7/10 ,  G11C7/06 ,  H03L7/081 ,  H04L27/00

CPC classification number: H04L7/0037 ,  G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C11/165 ,  G11C11/4093 ,  G11C11/4096 ,  H03L7/0812 ,  H04L27/0002

Abstract: Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.

Abstract translation: 描述了一种装置，包括：用于感测相对于另一信号的输入信号的输入感测级; 耦合到输入感测级的判定电路，用于确定输入信号是逻辑低还是逻辑高; 以及耦合到输入感测级和决策电路的电源管理电路，其可操作以监视决策电路的状态并根据监视状态禁用输入感测级。 描述了一种装置，其包括：与输入感测级集成的决策电路，其中所述决策电路可操作以在所述时钟信号的相位期间对其内部节点进行预充电; 以及锁存电路，用于锁存所述决策电路的输出。

公开(公告)号：US10333689B2

公开(公告)日：2019-06-25

申请号：US15262859

申请日：2016-09-12

Applicant: Intel Corporation

Inventor： Pankaj Vinayak Dudulwar ,  Chenchu Punnarao Bandi ,  Lip Khoon Teh ,  Tat Hin Tan

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/10 ,  H04L7/00 ,  G11C11/16 ,  H03L7/081 ,  H04L27/00 ,  G11C11/4093 ,  G11C11/4096

Abstract: Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.

公开(公告)号：US09443567B1

公开(公告)日：2016-09-13

申请号：US14688990

申请日：2015-04-16

Applicant: Intel Corporation

Inventor： Pankaj Vinayak Dudulwar ,  Chenchu Punnarao Bandi ,  Lip Khoon Teh ,  Tat Hin Tan

IPC: G11C7/06 ,  H04B1/16

CPC classification number: H04L7/0037 ,  G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C7/10 ,  G11C7/106 ,  G11C7/1078 ,  G11C11/165 ,  G11C11/4093 ,  G11C11/4096 ,  H03L7/0812 ,  H04L27/0002

Abstract: Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.

Abstract translation: 描述了一种装置，包括：用于感测相对于另一信号的输入信号的输入感测级; 耦合到输入感测级的判定电路，用于确定输入信号是逻辑低还是逻辑高; 以及耦合到输入感测级和决策电路的电源管理电路，其可操作以监视决策电路的状态并根据监视状态禁用输入感测级。 描述了一种装置，其包括：与输入感测级集成的决策电路，其中所述决策电路可操作以在所述时钟信号的相位期间对其内部节点进行预充电; 以及锁存电路，用于锁存所述决策电路的输出。