公开(公告)号：US08987859B2

公开(公告)日：2015-03-24

申请号：US13693602

申请日：2012-12-04

申请人： Intel Corporation

发明人： Pavel S. Plekhanov ,  Kevin J. Fischer ,  Qiang Fu ,  Hiroki Hiramatsu

IPC分类号： H01L21/70 ,  H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/48 ,  H01L21/768 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques are disclosed for enhancing the dielectric breakdown performance of integrated circuit (IC) interconnects. The disclosed techniques can be used to selectively etch the dielectric layer of an IC to form a recess, for example, between a given pair of adjacent/neighboring interconnects (e.g., metal lines). Thereafter, a layer of dielectric material of higher dielectric breakdown field (Ec) than the surrounding/underlying dielectric material (or other suitable insulator, as will be apparent in light of this disclosure) may be deposited/grown so as to substantially conform to the topology provided by the adjacent/neighboring interconnects and etched recess. In some cases, this dielectric layer may help to prevent or otherwise reduce: (1) dielectric breakdown between the adjacent/neighboring interconnects by locally increasing the dielectric breakdown voltage (VBD); and/or (2) diffusion of the interconnect fill metal into the surrounding/underlying dielectric material. In some instances, such a layer may serve as an etch stop.

摘要翻译： 公开了用于增强集成电路（IC）互连的介质击穿性能的技术。 所公开的技术可以用于选择性地蚀刻IC的电介质层，以形成例如在给定的一对相邻/相邻互连（例如，金属线）之间的凹部。 此后，可以沉积/生长比围绕/下面的电介质材料（或其他合适的绝缘体）更高的电介质击穿电场（Ec）的电介质材料层，以便基本上符合 拓扑由相邻/相邻互连和蚀刻凹槽提供。 在一些情况下，该介电层可以有助于防止或以其它方式减少：（1）通过局部增加介电击穿电压（VBD）来在相邻/相邻互连之间的介质击穿; 和/或（2）互连填充金属扩散到周围/下面的介电材料中。 在一些情况下，这样的层可以用作蚀刻停止。

公开(公告)号：US20230143021A1

公开(公告)日：2023-05-11

申请号：US17521760

申请日：2021-11-08

申请人： Intel Corporation

发明人： Daniel B. OBrien ,  Jeffrey S. Leib ,  James Y. Jeong ,  Chia-Hong Jan ,  Peng Bai ,  Seungdo An ,  Pavel S. Plekhanov ,  Debashish Basu

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L23/53266 ,  H01L23/53238 ,  H01L21/76877 ,  H01L21/76843

摘要： Integrated circuit interconnect structure compatible with single damascene techniques and that includes a non-copper via comprising metal(s) of low resistivity that can be deposited at low temperature in a manner that also ensures good adhesion. Metal(s) suitable for the non-copper via may have BCC crystallinity that can advantageously template favorable crystallinity within a diffusion barrier of the upper-level interconnect feature, further reducing electrical resistance of an interconnect structure.