公开(公告)号：US09716066B2

公开(公告)日：2017-07-25

申请号：US14779022

申请日：2013-06-29

申请人： Intel Corporation

发明人： Kevin J. Lee ,  James Y. Jeong ,  Hsiao-Kang Chang ,  John Muirhead ,  Adwait Telang ,  Puneesh Puri ,  Jiho Kang ,  Nitin M. Patel

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683

CPC分类号： H01L23/5384 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/564 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/03823 ,  H01L2224/03825 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/116 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16145 ,  H01L2924/13091 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014

摘要： A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

公开(公告)号：US12051623B2

公开(公告)日：2024-07-30

申请号：US17107717

申请日：2020-11-30

申请人： Intel Corporation

发明人： Seyedhamed M Barghi ,  Shyam Benegal Kadali ,  Marvin Y. Paik ,  Sheng-Po Fang ,  Leonard P. Guler ,  Charles H. Wallace ,  James Y. Jeong

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/311

CPC分类号： H01L21/76897 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816

摘要： Embodiments disclosed herein include methods of patterning a back end of line (BEOL) stack and the resulting structures. In an embodiment a method of patterning a BEOL stack comprises forming a grating over an interlayer dielectric (ILD), and forming a spacer over the grating. In an embodiment, the spacer is etch selective to the grating. In an embodiment, the method further comprises disposing a hardmask over the grating and the spacer, and patterning the hardmask to form an opening in the hardmask. In an embodiment, the method further comprises filling the opening with a plug, removing the hardmask, and etching the spacer. In an embodiment, a portion of the spacer is protected from the etch by the plug. In an embodiment, the method may further comprise removing the plug, and transferring the grating into the ILD with an etching process.

公开(公告)号：US09748180B2

公开(公告)日：2017-08-29

申请号：US15124820

申请日：2014-07-08

申请人： INTEL CORPORATION

发明人： Puneesh Puri ,  Jiho Kang ,  James Y. Jeong

IPC分类号： H01L29/00 ,  H01L23/00 ,  H01L21/762 ,  H01L29/06 ,  H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/562 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76897 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/05 ,  H01L29/0649 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques are disclosed for through-body via liner structures and processes of forming such liner structures in an integrated circuit. In an embodiment, an integrated circuit includes a silicon semiconductor substrate having one or more through-silicon vias (TSVs), although other through-body vias can be used as will be appreciated in light of this disclosure. Each TSV extends through at least a portion of the substrate, for example, from one side (e.g., top) of the substrate to the opposite side of the substrate (e.g., bottom), or from one internal layer of the substrate to another internal layer. A liner is disposed between the substrate and each TSV. The liner is formed of multiple alternating layers of dissimilar insulation films (e.g., tensile films and compressive films) sandwiched together.

公开(公告)号：US20230143021A1

公开(公告)日：2023-05-11

申请号：US17521760

申请日：2021-11-08

申请人： Intel Corporation

发明人： Daniel B. OBrien ,  Jeffrey S. Leib ,  James Y. Jeong ,  Chia-Hong Jan ,  Peng Bai ,  Seungdo An ,  Pavel S. Plekhanov ,  Debashish Basu

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L23/53266 ,  H01L23/53238 ,  H01L21/76877 ,  H01L21/76843

摘要： Integrated circuit interconnect structure compatible with single damascene techniques and that includes a non-copper via comprising metal(s) of low resistivity that can be deposited at low temperature in a manner that also ensures good adhesion. Metal(s) suitable for the non-copper via may have BCC crystallinity that can advantageously template favorable crystallinity within a diffusion barrier of the upper-level interconnect feature, further reducing electrical resistance of an interconnect structure.

公开(公告)号：US20160049371A1

公开(公告)日：2016-02-18

申请号：US14779022

申请日：2013-06-29

申请人： INTEL CORPORATION

发明人： Kevin J. Lee ,  James Y. Jeong ,  Hsiao-Kang Chang ,  John Muirhead ,  Adwait Telang ,  Puneesh Puri ,  Jiho Kang ,  Nitin M. Patel

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/5384 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/564 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/03823 ,  H01L2224/03825 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/116 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16145 ,  H01L2924/13091 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014

摘要： A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

摘要翻译： 描述了三维互连结构和制造方法，其中金属再分布层（RDL）与硅通孔（TSV）集成并且使用“平板通过抗蚀剂”型工艺流程。 氮化硅或碳化硅钝化层可以设置在薄化的器件晶片背面和RDL之间，以在工艺流程期间提供密封屏障和抛光停止层。