公开(公告)号：US10950198B2

公开(公告)日：2021-03-16

申请号：US15641463

申请日：2017-07-05

Applicant: Intel Corporation

Inventor： Aruna Kumar L S ,  Anoop Karunan ,  Sanjib Basu ,  Sunil Kumar C R

IPC: G09G5/00 ,  H04L29/06 ,  G09G5/36 ,  G09G3/20 ,  H04L7/00

Abstract: Embodiments include systems, devices, and methods for a combination CPHY/DPHY/eDP display transmission PHY. A CDE can include a MIPI display serial interface (DSI) circuitry configured to receive 8 bit data compliant with a DSI protocol and output a differential pair signal to a PISO circuit. The same data path is configured for incoming eDP data, which can be routed to circuitry configured to receive 10 bit data compliant with an eDP protocol and output a differential pair signal to a PISO circuit. The system can include a CPHY circuitry that includes a mapper circuit to map a 16 bit input to a 21 bit output, mapper circuit having three 7 bit outputs, and CPHY logic to output a trio. The MUX coupled to an output of the PISO is configured to output one of the eDP or the DSI or the CPHY data to an display driver.

公开(公告)号：US20220200780A1

公开(公告)日：2022-06-23

申请号：US17690339

申请日：2022-03-09

Applicant: Intel Corporation

Inventor： Per E. Fornberg ,  Anoop Karunan ,  Aruna Kumar L S ,  Sunil Kumar CR ,  Sleiman Bou-Sleiman

IPC: H04L7/00 ,  G06F13/42 ,  G06F1/26

Abstract: A system comprising transmission circuitry to communicate first data to receiver circuitry over a serial communication link during an active state of the serial communication link; and power adjustment circuitry to adjust a power level of the transmission circuitry responsive to a request based on at least one margin measurement performed by the receiver circuitry on the first data, wherein the transmission circuitry is to communicate second data using the adjusted power level over the serial communication link.

公开(公告)号：US10924305B2

公开(公告)日：2021-02-16

申请号：US16305116

申请日：2017-06-06

Applicant: Intel Corporation

Inventor： Aruna Kumar ,  Anoop Karunan ,  Ganesh Balamurugan ,  Prakash Radhakrishnan

IPC: H04L25/02 ,  H04L25/03 ,  H04L1/24 ,  H04L7/10 ,  H04L25/08 ,  H04N21/4363

Abstract: Disclosed herein are devices and methods to facilitate compensating for intra-pair skew in a high-definition multimedia interface (HDMI) system. One or more skew training pattern may be transmitted on a signal line including a differential pair. Acknowledgment of receiving the skew training pattern may be received on a display data channel (DDC) associated with HDMI system. The skew training pattern may be used to ascertain and compensate for intra-pair skew.

公开(公告)号：US20190012981A1

公开(公告)日：2019-01-10

申请号：US15641463

申请日：2017-07-05

Applicant: Intel Corporation

Inventor： Aruna Kumar L S ,  Anoop Karunan ,  Sanjib Basu ,  Sunil Kumar CR

IPC: G09G5/00 ,  H04L29/06

Abstract: Embodiments include systems, devices, and methods for a combination CPHY/DPHY/eDP display transmission PHY. A CDE can include a MIPI display serial interface (DSI) circuitry configured to receive 8 bit data compliant with a DSI protocol and output a differential pair signal to a PISO circuit. The same data path is configured for incoming eDP data, which can be routed to circuitry configured to receive 10 bit data compliant with an eDP protocol and output a differential pair signal to a PISO circuit. The system can include a CPHY circuitry that includes a mapper circuit to map a 16 bit input to a 21 bit output, mapper circuit having three 7 bit outputs, and CPHY logic to output a trio. The MUX coupled to an output of the PISO is configured to output one of the eDP or the DSI or the CPHY data to an display driver.