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    Confidential verification of FPGA code
    5.
    发明授权
    Confidential verification of FPGA code 有权

    公开(公告)号：US10972277B2

    公开(公告)日：2021-04-06

    申请号：US15459939

    申请日：2017-03-15

    申请人： INTEL CORPORATION

    发明人： Eric Innis ,  Raghunandan Makaram ,  Ting Lu

    IPC分类号： H04L29/06 ,  H04L9/32 ,  H04L29/08 ,  H04L9/08 ,  G06F21/76 ,  H04W4/60 ,  G06F21/57 ,  G06F21/60 ,  G06F21/62 ,  G06F21/64 ,  H04L9/06 ,  H04L9/14

    摘要： The present disclosure provides confidential verification for FPGA code. Confidential verification for FPGA code can include receiving the policy from a cloud service provider (CSP) computing device, wherein the policy comprises a plurality of policy requirements used to determine whether to configure the FPGA using the code, receiving the code and the code encryption key from the user computing device, determining whether the code fulfills the plurality of policy requirements, and when the code fulfills the plurality of policy requirements encrypting and integrity protect the code using the code encryption key and providing the encrypted and integrity protected code to an accelerator loader to configure the FPGA using the code.

    Cloud key management for AFU security
    6.
    发明授权
    Cloud key management for AFU security 有权

    公开(公告)号：US11489822B2

    公开(公告)日：2022-11-01

    申请号：US17063485

    申请日：2020-10-05

    申请人： Intel Corporation

    发明人： Brent D. Thomas ,  Eric Innis ,  Raghunandan Makaram

    IPC分类号： H04L9/40 ,  H04L9/32 ,  H04L9/30 ,  H04L9/08

    摘要： An apparatus for cloud key management may include a networking interface, a memory, and a processor, coupled to the memory and the networking interface, the networking interface to couple the apparatus to one or more endpoint servers (EPSs) of a cloud service provider (CSP), each EPS including a hardware accelerator, and a management node (MN) of the CSP. The apparatus may further include an accelerator functional unit (AFU) developer interface module operated by the processor to receive cryptographic material (CM) for each of one or more AFU developers (AFUDs) and store it into the memory, the CM includes a public key hash (PKH), and an encryption key (EK) to decrypt an AFU of the AFUD. The apparatus may also include an EK communication module operated by the processor to: receive, from the MN, a request to send to a targeted EPS an encrypted lookup table (LUT), the LUT including PKHs and associated EKs for a set of the one or more AFUDs from which the targeted EPS is authorized to receive AFUs, and in response to the request, send, to the targeted EPS, the LUT.

    Security Architecture for Partial Reconfiguration of a Configurable Integrated Circuit Die
    7.
    发明申请
    Security Architecture for Partial Reconfiguration of a Configurable Integrated Circuit Die 审中-公开

    公开(公告)号：US20200167506A1

    公开(公告)日：2020-05-28

    申请号：US16586131

    申请日：2019-09-27

    申请人： Intel Corporation

    发明人： Prakash Iyer ,  Eric Innis ,  Evan Custodio ,  Ting Lu

    IPC分类号： G06F21/76

    摘要： A PCIe card includes an FPGA and a memory that is discrete from the FPGA. The memory is accessible by the FPGA and not other devices on the card. The FPGA's core fabric is configured with a security processor that verifies a bitstream loaded through the FGPA into the memory as authentic or not authentic to limit unauthorized access to data from a user circuit that is associated with a not authentic bitstream. The security processor is loaded into the FPGA when a request is made for bitstream verification and is allowed to be overwritten after the security processor processes the bitstream to determine if the bitstream is authentication or not authentic. Allowing the security processor to be overwritten allows for high percentage usage of the core fabric for user circuits and limits the inclusion of a static circuit in the core fabric that is infrequently used.

    TECHNOLOGIES FOR SECURE AUTHENTICATION AND PROGRAMMING OF ACCELERATOR DEVICES
    8.
    发明申请
    TECHNOLOGIES FOR SECURE AUTHENTICATION AND PROGRAMMING OF ACCELERATOR DEVICES 审中-公开

    公开(公告)号：US20190132136A1

    公开(公告)日：2019-05-02

    申请号：US16232143

    申请日：2018-12-26

    申请人： Intel Corporation

    发明人： Vincent Scarlata ,  Reshma Lal ,  Alpa Narendra Trivedi ,  Eric Innis

    IPC分类号： H04L9/32 ,  H04L9/08 ,  G06F21/60 ,  G06F21/76

    摘要： Technologies for secure authentication and programming of an accelerator device include a computing device having a processor and an accelerator. The processor establishes a trusted execution environment, which receives a unique device identifier from the accelerator, validates a device certificate for the device identifier, authenticates the accelerator in response to validating the accelerator, validates attestation information of the accelerator, and establishes a secure channel with the accelerator. The trusted execution environment may securely program a data key and a bitstream key to the accelerator, and may encrypt a bitstream image and securely program the bitstream image to the accelerator. The accelerator and a tenant may securely exchange data protected by the data key. The trusted execution environment may be a secure enclave, and the accelerator may be a field programmable gate array (FPGA). Other embodiments are described and claimed.

    CLOUD KEY MANAGEMENT FOR AFU SECURITY
    9.
    发明申请
    CLOUD KEY MANAGEMENT FOR AFU SECURITY 有权

    公开(公告)号：US20210036998A1

    公开(公告)日：2021-02-04

    申请号：US17063485

    申请日：2020-10-05

    申请人： Intel Corporation

    发明人： Brent D. Thomas ,  Eric Innis ,  Raghunandan Makaram

    IPC分类号： H04L29/06 ,  H04L9/32 ,  H04L9/30 ,  H04L9/08

    摘要： An apparatus for cloud key management may include a networking interface, a memory, and a processor, coupled to the memory and the networking interface, the networking interface to couple the apparatus to one or more endpoint servers (EPSs) of a cloud service provider (CSP), each EPS including a hardware accelerator, and a management node (MN) of the CSP. The apparatus may further include an accelerator functional unit (AFU) developer interface module operated by the processor to receive cryptographic material (CM) for each of one or more AFU developers (AFUDs) and store it into the memory, the CM includes a public key hash (PKH), and an encryption key (EK) to decrypt an AFU of the AFUD. The apparatus may also include an EK communication module operated by the processor to: receive, from the MN, a request to send to a targeted EPS an encrypted lookup table (LUT), the LUT including PKHs and associated EKs for a set of the one or more AFUDs from which the targeted EPS is authorized to receive AFUs, and in response to the request, send, to the targeted EPS, the LUT.

    CLOUD KEY MANAGEMENT FOR AFU SECURITY
    10.
    发明申请
    CLOUD KEY MANAGEMENT FOR AFU SECURITY 审中-公开

    公开(公告)号：US20190044731A1

    公开(公告)日：2019-02-07

    申请号：US16017770

    申请日：2018-06-25

    申请人： Intel Corporation

    发明人： Brent D. Thomas ,  Eric Innis ,  Raghunandan Makaram

    IPC分类号： H04L9/32 ,  H04L9/30 ,  H04L29/06 ,  H04L9/08

    摘要： An apparatus for cloud key management may include a networking interface, a memory, and a processor, coupled to the memory and the networking interface, the networking interface to couple the apparatus to one or more endpoint servers (EPSs) of a cloud service provider (CSP), each EPS including a hardware accelerator, and a management node (MN) of the CSP. The apparatus may further include an accelerator functional unit (AFU) developer interface module operated by the processor to receive cryptographic material (CM) for each of one or more AFU developers (AFUDs) and store it into the memory, the CM includes a public key hash (PKH), and an encryption key (EK) to decrypt an AFU of the AFUD. The apparatus may also include an EK communication module operated by the processor to: receive, from the MN, a request to send to a targeted EPS an encrypted lookup table (LUT), the LUT including PKHs and associated EKs for a set of the one or more AFUDs from which the targeted EPS is authorized to receive AFUs, and in response to the request, send, to the targeted EPS, the LUT.