公开(公告)号：US20190235448A1

公开(公告)日：2019-08-01

申请号：US16370461

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Rajesh Banginwar ,  Ramkumar Jayaraman ,  Nabajit Deka ,  Riccardo Mariani

IPC: G05B9/02 ,  H04L12/40 ,  G06F13/40 ,  G06F9/54

CPC classification number: G05B9/02 ,  G06F9/541 ,  G06F13/4022 ,  G06F2213/0016 ,  G06F2213/0026 ,  G06F2213/0038 ,  H04L12/40 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: Methods and apparatus relating to enhancing diagnostic capabilities of computing systems by combining variable patrolling Application Program Interface (API) and comparison mechanism of variables are described. In one embodiment, a first processor core executes a first instance of a workload to generate a first set of safety variables. A second processor core executes a second instance of the workload to generate a second set of safety variables. A third processor core generates a signal in response to comparison of the first set of safety variables and the second set of safety variables. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190049916A1

公开(公告)日：2019-02-14

申请号：US16155495

申请日：2018-10-09

Applicant: Intel Corporation

Inventor： Nabajit Deka ,  Riccardo Mariani ,  Asad Azam ,  Rajesh Banginwar ,  Wenjun Zhang

IPC: G05B19/042

Abstract: An apparatus of a System on Chip (SoC) to implement a one out of two diagnostics (1oo2D) safety system comprises a memory comprising firmware to provide monitoring of the SoC and a second SoC, and a communication interface to provide cross-monitoring between the SoC and the second SoC. The firmware and the communication interface enable the SoC and the second SoC to implement the 1oo2D safety system without significant hardware or software external to the SoC.

公开(公告)号：US11520297B2

公开(公告)日：2022-12-06

申请号：US16370461

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Rajesh Banginwar ,  Ramkumar Jayaraman ,  Nabajit Deka ,  Riccardo Mariani

IPC: G06F13/40 ,  G05B9/02 ,  H04L12/40 ,  G06F9/54 ,  G06F11/30

Abstract: Methods and apparatus relating to enhancing diagnostic capabilities of computing systems by combining variable patrolling Application Program Interface (API) and comparison mechanism of variables are described. In one embodiment, a first processor core executes a first instance of a workload to generate a first set of safety variables. A second processor core executes a second instance of the workload to generate a second set of safety variables. A third processor core generates a signal in response to comparison of the first set of safety variables and the second set of safety variables. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240106644A1

公开(公告)日：2024-03-28

申请号：US17954157

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Aditya Katragada ,  Geoffrey Strongin ,  Prakash Iyer ,  Rajesh Banginwar ,  Poh Thiam Teoh ,  Gary Wallichs

IPC: H04L9/08

CPC classification number: H04L9/0891 ,  H04L9/0894

Abstract: A system and method of enhancing the mitigation of side channel attacks on platform interconnects using endpoint HW based detection, synchronization, and re-keying include generating a set of keys for link encryption based on a high entropy seed, storing the set of keys in a deterministic order in a register, detecting that a re-key programmable threshold is met during link encryption with a device, identifying a synchronization point associated with the device, where the synchronization point indicates the device is ready to switch a current key used for link encryption, and synchronizing a rekeying event with the device.

公开(公告)号：US10955805B2

公开(公告)日：2021-03-23

申请号：US16155495

申请日：2018-10-09

Applicant: Intel Corporation

Inventor： Nabajit Deka ,  Riccardo Mariani ,  Asad Azam ,  Rajesh Banginwar ,  Wenjun Zhang

IPC: G06F11/00 ,  G05B19/042 ,  G06F11/07

Abstract: An apparatus of a System on Chip (SoC) to implement a one out of two diagnostics (1oo2D) safety system comprises a memory comprising firmware to provide monitoring of the SoC and a second SoC, and a communication interface to provide cross-monitoring between the SoC and the second SoC. The firmware and the communication interface enable the SoC and the second SoC to implement the 1oo2D safety system without significant hardware or software external to the SoC.