公开(公告)号：US20240063072A1

公开(公告)日：2024-02-22

申请号：US17891530

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Shawna Liff ,  Kimin Jun ,  Veronica Strong ,  Aleksandar Aleksov ,  Jiraporn Seangatith ,  Mohammad Enamul Kabir ,  Johanna Swan ,  Tushar Talukdar ,  Omkar Karhade

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L23/3135 ,  H01L25/0652 ,  H01L25/0655 ,  H01L23/49816 ,  H01L23/49838 ,  H01L21/568 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/291 ,  H01L24/08

Abstract: Composite integrated circuit (IC) device processing, including selective removal of inorganic dielectric material. Inorganic dielectric material may be deposited, modified with laser exposure, and selectively removed. Laser exposure parameters may be adjusted using surface topography measurements. Inorganic dielectric material removal may reduce surface topography. Vias and trenches of varying size, shape, and depth may be concurrently formed without an etch-stop layer. A composite IC device may include an IC die, a conductive via, and a conductive line adjacent a compositionally homogenous inorganic dielectric material.

公开(公告)号：US20240063147A1

公开(公告)日：2024-02-22

申请号：US17891704

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Mohammad Enamul Kabir ,  Johanna Swan ,  Omkar Karhade ,  Kimin Jun ,  Feras Eid ,  Shawna Liff ,  Xavier Brun ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Haris Khan Niazi

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L23/564 ,  H01L24/08 ,  H01L24/24 ,  H01L25/0652 ,  H01L24/19 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/291 ,  H01L2224/08145 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/37001 ,  H01L2224/24145 ,  H01L24/73 ,  H01L2224/73259 ,  H01L2224/24225 ,  H01L2224/73209 ,  H01L2224/2499

Abstract: Techniques and mechanisms to mitigate corrosion to via structures of a composite chiplet. In an embodiment, a composite chiplet comprises multiple integrated circuit (IC) components which are each in a different respective one of multiple levels. One or more conductive vias extend through an insulator layer in a first level of the multiple levels. An annular structure of the composite chiplet extends vertically through the insulator layer, and surrounds the one or more conductive vias in the insulator layer. The annular structure mitigates an exposure of the one or more conductive vias to moisture which is in a region of the insulator layer that is not surrounded by the annular structure. In another embodiment, the annular structure further surrounds an IC component which extends in the insulator layer.

公开(公告)号：US20240063076A1

公开(公告)日：2024-02-22

申请号：US17891727

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Mohammad Enamul Kabir ,  Bhaskar Jyoti Krishnatreya ,  Kimin Jun ,  Adel Elsherbini ,  Tushar Talukdar ,  Feras Eid ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Xavier Brun

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/373 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/367 ,  H01L24/08 ,  H01L23/3736 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/481 ,  H01L24/32 ,  H01L24/29 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/32225 ,  H01L2224/29147 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29193 ,  H01L2224/29186

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die, a conformal thermal heat spreading layer on the top and sidewalls of the integrated circuit dies, and an inorganic dielectric material on a portion of the conformal thermal heat spreading layer, laterally adjacent the integrated circuit dies, and over the base die. The conformal thermal heat spreading layer includes a high thermal conductivity material to provide a thermal pathway for the integrated circuit dies during operation.

公开(公告)号：US12148747B2

公开(公告)日：2024-11-19

申请号：US17033513

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Pratik Koirala ,  Nicole K. Thomas ,  Paul B. Fischer ,  Adel A. Elsherbini ,  Tushar Talukdar ,  Johanna M. Swan ,  Wilfred Gomes ,  Robert S. Chau ,  Beomseok Choi

IPC: H01L27/06 ,  H01L21/765 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20240063180A1

公开(公告)日：2024-02-22

申请号：US17891654

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Adel Elsherbini ,  Omkar Karhade ,  Bhaskar Jyoti Krishnatreya ,  Mohammad Enamul Kabir ,  Jiraporn Seangatith ,  Tushar Talukdar ,  Shawna Liff ,  Johanna Swan ,  Feras Eid

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/3185 ,  H01L24/05

Abstract: Quasi-monolithic multi-die composites including a primary fill structure within a space between adjacent IC dies. A fill material layer, which may have inorganic composition, may be bonded to a host substrate and patterned to form a primary fill structure that occupies a first portion of the host substrate. IC dies may be bonded to regions of the host substrate within openings where the primary fill structure is absent to have a spatial arrangement complementary to the primary fill structure. The primary fill structure may have a thickness substantially matching that of IC dies and/or be co-planar with a surface of one or more of the IC dies. A gap fill material may then be deposited within remnants of the openings to form a secondary fill structure that occupies space between the IC dies and the primary fill structure.

公开(公告)号：US20240063066A1

公开(公告)日：2024-02-22

申请号：US17891665

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Tomita Yoshihiro ,  Adel A. Elsherbini ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Haris Khan Niazi ,  Yi Shi ,  Batao Zhang ,  Wenhao Li ,  Feras Eid

IPC: H01L23/04 ,  H01L25/065 ,  H01L23/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/46 ,  H01L23/367

CPC classification number: H01L23/041 ,  H01L25/0652 ,  H01L23/18 ,  H01L24/08 ,  H01L23/481 ,  H01L23/46 ,  H01L23/367 ,  H01L2224/08145 ,  H01L2224/05599 ,  H01L24/05 ,  H01L2224/80379 ,  H01L24/80 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73 ,  H01L2224/131 ,  H01L24/13 ,  H01L2224/29099 ,  H01L24/29

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a template structure having a first surface and an opposing second surface, wherein the first surface of the template structure is coupled to the surface of the first die, and wherein the template structure includes a cavity at the first surface and a through-template opening extending from a top surface of the cavity to the second surface of the template structure; and a second die within the cavity of the template structure and electrically coupled to the surface of the first die by interconnects having a pitch of less than 10 microns between adjacent interconnects.

公开(公告)号：US20240063178A1

公开(公告)日：2024-02-22

申请号：US17821001

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Adel A. Elsherbini ,  Xavier Francois Brun ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Yi Shi ,  Tushar Talukdar ,  Feras Eid ,  Mohammad Enamul Kabir ,  Omkar G. Karhade ,  Bhaskar Jyoti Krishnatreya

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3107 ,  H01L24/16 ,  H01L24/08 ,  H01L2225/06548 ,  H01L2224/16227 ,  H01L2224/08145 ,  H01L2224/13116 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13109 ,  H01L2224/13118 ,  H01L24/13 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05613 ,  H01L2224/05609 ,  H01L2224/05605 ,  H01L24/05

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die and a through-dielectric via (TDV) surrounded by a dielectric material in a first layer, where the TDV has a greater width at a first surface and a smaller width at an opposing second surface of the first layer; a second die, surrounded by the dielectric material, in a second layer on the first layer, where the first die is coupled to the second die by interconnects having a pitch of less than 10 microns, and the dielectric material around the second die has an interface seam extending from a second surface of the second layer towards an opposing first surface of the second layer with an angle of less than 90 degrees relative to the second surface; and a substrate on and coupled to the second layer.

公开(公告)号：US20240063143A1

公开(公告)日：2024-02-22

申请号：US17891690

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Lance C. Hibbeler ,  Omkar Karhade ,  Chytra Pawashe ,  Kimin Jun ,  Feras Eid ,  Shawna Liff ,  Mohammad Enamul Kabir ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Wenhao Li

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L25/0657 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2924/3511

Abstract: Techniques and mechanisms to mitigate warping of a composite chiplet. In an embodiment, multiple via structures each extend through an insulator material in one of multiple levels of a composite chiplet. The insulator material extends around an integrated circuit (IC) component in the level. For a given one of the multiple via structures, a respective annular structure extends around the via structure to mitigate a compressive (or tensile) stress due to expansion (or contraction) of the via structure. In another embodiment, the composite chiplet additionally or alternatively comprises a structural support layer on the multiple levels, wherein the structural support layer has formed therein or thereon dummy via structures or a warpage compensation film.

公开(公告)号：US20240063142A1

公开(公告)日：2024-02-22

申请号：US17891666

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Botao Zhang ,  Yi Shi ,  Haris Khan Niazi ,  Feras Eid ,  Nagatoshi Tsunoda ,  Xavier Brun ,  Mohammad Enamul Kabir ,  Omkar Karhade ,  Shawna Liff ,  Jiraporn Seangatith

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L23/367 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L21/486 ,  H01L21/565 ,  H01L25/0655 ,  H01L25/50

Abstract: Multi-die packages including IC die crack mitigation features. Prior to the bonding of IC dies to a host substrate, the IC dies may be shaped, for example with a corner radius or chamfer. After bonding the shaped IC dies, a fill comprising at least one inorganic material may be deposited over the IC dies, for example to backfill a space between adjacent IC dies. With the benefit of a greater IC die sidewall slope and/or smoother surface topology associated with the shaping process, occurrences of stress cracking within the fill and concomitant damage to the IC dies may be reduced. Prior to depositing a fill, a barrier layer may be deposited over the IC die to prevent cracks that might form in the fill material from propagating into the IC die.

公开(公告)号：US20240063089A1

公开(公告)日：2024-02-22

申请号：US17891738

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Lei Jiang ,  Yoshihiro Tomita ,  Omkar Karhade ,  Haris Khan Niazi ,  Tushar Talukdar ,  Mohammad Enamul Kabir ,  Xavier Brun ,  Feras Eid

IPC: H01L23/46

CPC classification number: H01L23/46 ,  G02B6/4268

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die and an inorganic dielectric material adjacent the integrated circuit dies and over the base die. The multichip composite device includes a dummy die, dummy vias, or integrated fluidic cooling channels laterally adjacent the integrated circuit dies to conduct heat from the base die.