公开(公告)号：US20190250916A1

公开(公告)日：2019-08-15

申请号：US16336884

申请日：2016-09-30

申请人： Intel Corporation

发明人： Patrick LU ,  Karthik KUMAR ,  Thomas WILLHALM ,  Francesc GUIM BERNAT ,  Martin P. DIMITROV

IPC分类号： G06F9/30 ,  G06F12/0862 ,  G06F12/0811

CPC分类号： G06F9/30047 ,  G06F9/30043 ,  G06F9/383 ,  G06F12/0811 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2212/205 ,  G06F2212/6028

摘要： An apparatus is described. The apparatus includes main memory control logic circuitry comprising prefetch intelligence logic circuitry. The prefetch intelligence circuitry to determine, from a read result of a load instruction, an address for a dependent load that is dependent on the read result and direct a read request for the dependent load to a main memory to fetch the dependent load's data.

公开(公告)号：US20210042228A1

公开(公告)日：2021-02-11

申请号：US17069819

申请日：2020-10-13

申请人： Intel Corporation

发明人： Andrew J. HERDRICH ,  Priya AUTEE ,  Abhishek KHADE ,  Patrick LU ,  Edwin VERPLANKE ,  Vedvyas SHANBHOGUE

IPC分类号： G06F12/0811 ,  G06F12/0891 ,  G06F12/06 ,  G06F12/1027 ,  G06F12/14 ,  G06F9/30 ,  G06F9/455

摘要： Examples provide a system that includes at least one processor; a cache; a memory; an interface to copy data from a received packet to the memory or the at least one cache; and controller to manage use of at least one region of the cache. In some examples, the controller is to: indicate availability of a cache region reservation feature; receive a request to reserve a region of the cache from a requester; and based on the requested region being permitted to be reserved by the requester, solely allow the requester to write data to at least a portion of the reserved region. In some examples, the controller is to write to a register to indicate availability of a cache region reservation feature. In some examples, the request to reserve a region of the cache from a requester comprises a specification of a number of sets, a number of ways, and a class of service.

公开(公告)号：US20190340123A1

公开(公告)日：2019-11-07

申请号：US16514226

申请日：2019-07-17

申请人： Intel Corporation

发明人： Andrew J. HERDRICH ,  Priya AUTEE ,  Abhishek KHADE ,  Patrick LU ,  Edwin VERPLANKE ,  Vivekananthan SANJEEPAN

IPC分类号： G06F12/0802

摘要： Examples provide an application program interface or manner of negotiating locking or pinning or unlocking or unpinning of a cache region by which an application, software, or hardware. A cache region can be part of a level-1, level-2, lower or last level cache (LLC), or translation lookaside buffer (TLB) are locked (e.g., pinned) or unlocked (e.g., unpinned). A cache lock controller can respond to a request to lock or unlock a region of cache or TLB by indicating that the request is successful or not successful. If a request is not successful, the controller can provide feedback indicating one or more aspects of the request that are not permitted. The application, software, or hardware can submit another request, a modified request, based on the feedback to attempt to lock a portion of the cache or TLB.