Abstract:
Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.
Abstract:
Methods and apparatus to accelerate boot time zeroing of memory based on Non-Volatile Memory (NVM) technology are described. In an embodiment, a storage device stores a boot version number corresponding to a portion of a non-volatile memory. A memory controller logic causes an update of the stored boot version number in response to each subsequent boot event. The memory controller logic returns a zero in response to a read operation directed at the portion of the non-volatile memory and a mismatch between the stored boot version number and a current boot version number. Other embodiments are also disclosed and claimed.