公开(公告)号：US20180137668A1

公开(公告)日：2018-05-17

申请号：US15811459

申请日：2017-11-13

Applicant: Intel Corporation

Inventor： Pietro Mercati ,  Raid Ayoub ,  Michael Kishinevsky ,  Eric C. Samson ,  Marc Beuchat ,  Francesco Paterna

IPC: G06T15/00 ,  G06T15/80

CPC classification number: G06T15/005 ,  G06F1/206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F8/41 ,  G06F8/65 ,  G06T15/80 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/42

Abstract: Methods and apparatus relating to techniques for dynamically selecting optimum graphics logic frequency and/or graphics logic power gating configuration are described. In an embodiment, multi-rate control logic determines processor active slice count and processor frequency based at least in part on a target Frames Per Second (FPS) value and a current FPS value. The multi-rate control logic includes slow rate control logic to determine slice gating and operating frequency and a fast rate control logic to determine operating frequency of the processor. Other embodiments are also disclosed and claimed.