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公开(公告)号：US20210266836A1
公开(公告)日：2021-08-26
申请号：US17307816
申请日：2021-05-04
Applicant: Intel Corporation
Inventor： Eric C. Samson , Murali Ramadoss , Marc Beuchat
IPC: H04W52/02 , H04W52/18 , G06T1/20 , G06F1/324 , G06F1/3234
Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.
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公开(公告)号：US10178619B1
公开(公告)日：2019-01-08
申请号：US15720906
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Eric C. Samson , Murali Ramadoss , Marc Beuchat
Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.
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3.发明申请公开(公告)号：US20160357241A1
公开(公告)日：2016-12-08
申请号：US14731162
申请日：2015-06-04
Applicant: Intel Corporation
Inventor： Murali Ramadoss , Marc Beuchat
CPC classification number: G06F1/3293 , G06F1/3228 , G06F1/329 , G06F9/5027 , G06F2209/509 , G06T1/20 , Y02D10/122 , Y02D10/24
Abstract: One or more system, apparatus, method, and computer readable media is described below for power management of one or more graphics processor resources. In some embodiments, a graphics processor context associated with an application an including power-related hardware configuration and control parameters is stored to memory. In some embodiments, graphics processor contexts are switched in and out as different application workloads are processed by resources of the graphics processor. In some embodiments, power-performance management algorithms are grouped and sequentially executed in ordered phases of a control loop to generate a compatible set of control parameter requests. Once finalized, the set is output as requests to graphics processor hardware and/or updates to stored graphics processor contexts.
Abstract translation: 下面描述一个或多个系统，装置，方法和计算机可读介质，用于一个或多个图形处理器资源的电源管理。 在一些实施例中，将与包括电力相关的硬件配置和控制参数的应用相关联的图形处理器上下文存储到存储器。 在一些实施例中，随着不同的应用工作负载由图形处理器的资源处理，图形处理器上下文被切换进出。 在一些实施例中，功率 - 性能管理算法在控制环路的有序阶段被分组并依次执行，以产生一组兼容的控制参数请求。 一旦最终确定，该集合作为对图形处理器硬件的请求和/或对存储的图形处理器上下文的更新输出。
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公开(公告)号：US12253901B2
公开(公告)日：2025-03-18
申请号：US17490290
申请日：2021-09-30
Applicant: Intel Corporation
Inventor： Nikos Kaburlasos , Rodrigo De Oliveira Vivi , Phani Kumar Kandula , Marc Beuchat , Mark J. Luckeroth , Eric J. M. Moret , David N. Lombard , John Kelbert , Brad Bittel
IPC: G06F1/32 , G06F1/08 , G06F1/3228 , G06F1/3296
Abstract: Disclosed herein are embodiments of systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices. In an embodiment, a processor includes a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution. The processor also includes temperature-measurement circuitry configured to monitor an on-chip temperature of the processor. The processor also includes control logic configured to: determine whether the processor is active or idle; determine whether the on-chip temperature of the processor exceeds a first threshold; based on determining that the processor is idle and that the on-chip temperature of the processor exceeds the first threshold, disable one or more idle-mode power-saving features of the processor; and selectively adjust one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second (higher) threshold.
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公开(公告)号：US10560892B2
公开(公告)日：2020-02-11
申请号：US16243029
申请日：2019-01-08
Applicant: Intel Corporation
Inventor： Eric C. Samson , Murali Ramadoss , Marc Beuchat
Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.
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Patent Agency Ranking
公开(公告)号：US10162405B2
公开(公告)日：2018-12-25
申请号：US14731162
申请日：2015-06-04
Applicant: Intel Corporation
Inventor： Murali Ramadoss , Marc Beuchat
Abstract: One or more system, apparatus, method, and computer readable media is described below for power management of one or more graphics processor resources. In some embodiments, a graphics processor context associated with an application an including power-related hardware configuration and control parameters is stored to memory. In some embodiments, graphics processor contexts are switched in and out as different application workloads are processed by resources of the graphics processor. In some embodiments, power-performance management algorithms are grouped and sequentially executed in ordered phases of a control loop to generate a compatible set of control parameter requests. Once finalized, the set is output as requests to graphics processor hardware and/or updates to stored graphics processor contexts.
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公开(公告)号：US11533683B2
公开(公告)日：2022-12-20
申请号：US17307816
申请日：2021-05-04
Applicant: Intel Corporation
Inventor： Eric C. Samson , Murali Ramadoss , Marc Beuchat
Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.
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公开(公告)号：US11127106B2
公开(公告)日：2021-09-21
申请号：US16456618
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Murali Ramadoss , Ankur Shah , Marc Beuchat
Abstract: Methods and apparatus relating to techniques for runtime flip stability characterization are described. In an embodiment, logic circuitry determines the amount of work to be performed by a processor to render a pattern during each of a plurality of Vertical blank (Vblank) intervals. Memory stores information corresponding to a workload to be executed by the processor during each of the plurality of Vblank intervals. An operating frequency of the processor may then be modified based at least in part on analysis of the stored information to indicate which of the plurality of Vblank intervals would provide an improved stability for rendering the pattern. Other embodiments are also disclosed and claimed.
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公开(公告)号：US10999797B2
公开(公告)日：2021-05-04
申请号：US16783076
申请日：2020-02-05
Applicant: Intel Corporation
Inventor： Eric C. Samson , Murali Ramadoss , Marc Beuchat
Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.
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10.发明申请公开(公告)号：US20180137668A1
公开(公告)日：2018-05-17
申请号：US15811459
申请日：2017-11-13
Applicant: Intel Corporation
Inventor： Pietro Mercati , Raid Ayoub , Michael Kishinevsky , Eric C. Samson , Marc Beuchat , Francesco Paterna
CPC classification number: G06T15/005 , G06F1/206 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F8/41 , G06F8/65 , G06T15/80 , Y02D10/126 , Y02D10/16 , Y02D10/171 , Y02D10/172 , Y02D10/42
Abstract: Methods and apparatus relating to techniques for dynamically selecting optimum graphics logic frequency and/or graphics logic power gating configuration are described. In an embodiment, multi-rate control logic determines processor active slice count and processor frequency based at least in part on a target Frames Per Second (FPS) value and a current FPS value. The multi-rate control logic includes slow rate control logic to determine slice gating and operating frequency and a fast rate control logic to determine operating frequency of the processor. Other embodiments are also disclosed and claimed.
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