公开(公告)号：US20220310610A1

公开(公告)日：2022-09-29

申请号：US17213144

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Rajat PAUL

IPC: H01L27/108 ,  H01L49/02 ,  H01L27/01 ,  H01L23/522 ,  H01L29/786

Abstract: Thin-film transistors and MIM capacitors in exclusion zones are described. In an example, an integrated circuit structure includes a semiconductor substrate having a zone with metal oxide semiconductor (MOS) transistors therein, and having a zone that excludes MOS transistors. A back-end-of-line (BEOL) structure is above the semiconductor substrate. A thin-film transistor (TFT) and/or a metal-insulator-metal (MIM) capacitor is in the BEOL structure. The TFT and/or MIM capacitor is vertically over the zone that excludes MOS transistors.

公开(公告)号：US20220190159A1

公开(公告)日：2022-06-16

申请号：US17122907

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Rajat PAUL ,  Willy RACHMADY ,  Jessica TORRES ,  Rambert NAHM ,  Ashish AGRAWAL ,  Siddharth CHOUKSEY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/165 ,  H01L29/66 ,  H01L27/12

Abstract: Integrated circuit structures having GeSnB source or drain structures, and methods of fabricating integrated circuit structures having GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include germanium, tin and boron.

公开(公告)号：US20200006570A1

公开(公告)日：2020-01-02

申请号：US16024687

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Van H. LE ,  Rajat PAUL ,  Abhishek SHARMA ,  Tahir GHANI ,  Jack KAVALIEROS ,  Gilbert DEWEY ,  Matthew METZ ,  Miriam RESHOTKO ,  Benjamin CHU-KUNG ,  Justin WEBER ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/45

Abstract: Embodiments of the present disclosure are contact structures for thin film transistor (TFT) devices. One embodiment is a TFT device comprising: a substrate; a gate formed above the substrate; a TFT channel formed above the substrate; and a pair of contacts formed on the TFT channel, wherein each of the contacts comprises one or more layers including: a metal that is non-reactive with a material of the TFT channel; or a plurality of layers including a first metal layer formed on a second layer, the second layer in contact with the TFT channel and between the first mater layer and the TFT channel. Other embodiments may be disclosed and/or claimed.