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    PRIORITY BASED APPLICATION EVENT CONTROL (PAEC) TO REDUCE POWER CONSUMPTION
    1.
    发明申请
    PRIORITY BASED APPLICATION EVENT CONTROL (PAEC) TO REDUCE POWER CONSUMPTION 审中-公开
    基于优先级的应用事件控制（PAEC）降低功耗

    公开(公告)号：US20160252951A1

    公开(公告)日：2016-09-01

    申请号：US15153995

    申请日：2016-05-13

    Applicant: Intel Corporation

    Inventor： Rajesh Poornachandran ,  Rajeev Muralidhar

    IPC: G06F1/32

    CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3234

    Abstract: Methods and apparatus relating to Priority Based Application Event Control (PAEC) to reduce application events are described. In one embodiment, PAEC may determine which applications (and their corresponding sub-system(s)) may cause a processor or platform to exit a low power consumption state. In an embodiment, PAEC may determine which applications (and their corresponding sub-system(s)) may resume operations after a processor or platform exit a low power consumption state. Other embodiments are also claimed and disclosed.

    Abstract translation: 描述了与基于优先级的应用事件控制（PAEC）相关的减少应用事件的方法和设备。 在一个实施例中，PAEC可以确定哪些应用程序（及其相应的子系统）可能导致处理器或平台退出低功耗状态。 在一个实施例中，PAEC可以在处理器或平台退出低功耗状态之后确定哪些应用（及其相应的子系统）可以恢复操作。 还要求和公开其它实施例。

    Trace hub logic with automatic event triggering
    4.
    发明授权
    Trace hub logic with automatic event triggering 有权

    公开(公告)号：US10534688B2

    公开(公告)日：2020-01-14

    申请号：US15420612

    申请日：2017-01-31

    Applicant: INTEL CORPORATION

    Inventor： Brinda Kh ,  Ravish Kumar ,  Rajeev Muralidhar

    IPC: G06F11/30 ,  G06F11/34

    Abstract: Technologies for execution trace with automatic event triggering include a computing device that includes an execution trace hub. The trace hub observes execution trace packets and determines whether the execution trace packets match one or more event trigger rules. If an execution packet matches an event trigger rule, the trace hub invokes an event callback. The event callback may be a predefined hardware function of the computing device or a software function. The trace hub may be configured with event trigger rules and associated event callbacks, for example by writing to one or more corresponding configuration space registers. In response to invoking the event callback, the computing device may, for example, output state information of the computing device to a data storage device, halt execution, activate a debug mode of the processor, or execute a software recovery function. Other embodiments are described and claimed.

    Priority Based Application Event Control (PAEC) To Reduce Power Consumption
    5.
    发明申请
    Priority Based Application Event Control (PAEC) To Reduce Power Consumption 审中-公开

    公开(公告)号：US20190294231A1

    公开(公告)日：2019-09-26

    申请号：US16373839

    申请日：2019-04-03

    Applicant: Intel Corporation

    Inventor： Rajesh Poornachandran ,  Rajeev Muralidhar

    IPC: G06F1/3287 ,  G06F1/3234 ,  G06F1/3206

    Abstract: Methods and apparatus relating to Priority Based Application Event Control (PAEC) to reduce application events are described. In one embodiment, PAEC may determine which applications (and their corresponding sub-system(s)) may cause a processor or platform to exit a low power consumption state. In an embodiment, PAEC may determine which applications (and their corresponding sub-system(s)) may resume operations after a processor or platform exit a low power consumption state. Other embodiments are also claimed and disclosed.

    Power governance of processing unit
    6.
    发明授权
    Power governance of processing unit 有权

    公开(公告)号：US11132046B2

    公开(公告)日：2021-09-28

    申请号：US16650782

    申请日：2017-12-15

    Applicant: Intel Corporation

    Inventor： Barnes Cooper ,  Harinarayanan Seshadri ,  Rajeev Muralidhar ,  Noor Mubeen

    IPC: G06F1/32 ,  G06F1/3228 ,  G06F1/329 ,  G06F1/3296

    Abstract: Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

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