公开(公告)号：US20170236566A1

公开(公告)日：2017-08-17

申请号：US15046384

申请日：2016-02-17

Applicant: Intel Corporation

Inventor： Pooja Nukala ,  Christopher Mozak ,  Kristina D. Morgan ,  Rebecca Loop

IPC: G11C7/10 ,  G06F13/16

CPC classification number: G11C7/1072 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/4243 ,  G06F13/4291

Abstract: Memory devices, systems, and methods that maximize command and address (CA) signal group rate with minimized margin degradation across a channel and associated operating modes are disclosed and described. In one example, the operating mode can be 1 bit per 1.5 clock cycles.