公开(公告)号：US20170288647A1

公开(公告)日：2017-10-05

申请号：US15087250

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Sameer Shekhar ,  Amit K. Jain ,  Pooja Nukala

IPC: H03K3/011 ,  H01L25/065 ,  H05K1/18 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L23/49838 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1432 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19043 ,  H01L2924/19101 ,  H03K19/0005 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/10234 ,  H05K2201/10318 ,  H05K2201/10378

Abstract: Some embodiments include apparatus and methods using a package substrate and a die coupled to the package substrate. The package substrate includes conductive contacts, conductive paths coupled to the conductive contacts, and a resistor embedded in the package substrate. The die includes buffer circuits and a calibration module coupled to the buffer circuits and the resistor. The buffer circuits include output nodes coupled to the conductive contacts through the conductive paths. The calibration module is configured to perform a calibration operation to adjust resistances of the buffer circuits based on a value of a voltage at a terminal of the resistor during the calibration operation.

公开(公告)号：US09813046B2

公开(公告)日：2017-11-07

申请号：US15087250

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Sameer Shekhar ,  Amit K. Jain ,  Pooja Nukala

IPC: H03K3/011 ,  H01L23/00 ,  H01L23/498 ,  H05K1/18 ,  H01L25/065

CPC classification number: H01L25/0655 ,  H01L23/49838 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1432 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19043 ,  H01L2924/19101 ,  H03K19/0005 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/10234 ,  H05K2201/10318 ,  H05K2201/10378

Abstract: Some embodiments include apparatus and methods using a package substrate and a die coupled to the package substrate. The package substrate includes conductive contacts, conductive paths coupled to the conductive contacts, and a resistor embedded in the package substrate. The die includes buffer circuits and a calibration module coupled to the buffer circuits and the resistor. The buffer circuits include output nodes coupled to the conductive contacts through the conductive paths. The calibration module is configured to perform a calibration operation to adjust resistances of the buffer circuits based on a value of a voltage at a terminal of the resistor during the calibration operation.

公开(公告)号：US20170236566A1

公开(公告)日：2017-08-17

申请号：US15046384

申请日：2016-02-17

Applicant: Intel Corporation

Inventor： Pooja Nukala ,  Christopher Mozak ,  Kristina D. Morgan ,  Rebecca Loop

IPC: G11C7/10 ,  G06F13/16

CPC classification number: G11C7/1072 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/4243 ,  G06F13/4291

Abstract: Memory devices, systems, and methods that maximize command and address (CA) signal group rate with minimized margin degradation across a channel and associated operating modes are disclosed and described. In one example, the operating mode can be 1 bit per 1.5 clock cycles.