公开(公告)号：US20200286543A1

公开(公告)日：2020-09-10

申请号：US16741368

申请日：2020-01-13

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Christopher P. MOZAK ,  Christopher E. COX ,  Yan FU ,  Robert J. FRIAR ,  Hsien-Pao YANG

IPC: G11C11/4072 ,  G06F3/06 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4076 ,  G06F13/16

Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

公开(公告)号：US20210074333A1

公开(公告)日：2021-03-11

申请号：US17086220

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Chong J. ZHAO ,  James A. McCALL ,  Robert J. FRIAR ,  Yidnekachew S. MEKONNEN ,  San K. CHHAY

IPC: G11C5/06 ,  G11C8/18 ,  H05K5/02

Abstract: Examples described herein relate to a pattern of pins where the signals assigned to the pins are arranged in a manner to reduce cross-talk. In some examples, a socket substrate includes a first group of pins that includes a first group of data (DQ) pins separated by at least two Voltage Source Supply (VSS) pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, data strobe signal (DQS) pins are positioned in a column between the first and third groups of DQ pins and the second and fourth groups of DQ pins. In some examples, a second group of pins includes a first group of DQ pins separated by at least two VSS pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, the second group of pins, DQS pins are positioned between the first and third groups of DQ pins and the second and fourth groups of DQ pins.

公开(公告)号：US20190096468A1

公开(公告)日：2019-03-28

申请号：US15716485

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Christopher P. MOZAK ,  Christopher E. COX ,  Yan FU ,  Robert J. FRIAR ,  Hsien-Pao YANG

IPC: G11C11/4072 ,  G06F3/06

Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.