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1.发明授权公开(公告)号：US10756747B2
公开(公告)日：2020-08-25
申请号：US16459421
申请日：2019-07-01
Applicant: Intel Corporation
Inventor： Roee Eitan , Ram Livne , Ahmad Khairi , Yoel Krupnik , Ariel Cohen
Abstract: An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.
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公开(公告)号：US10855305B2
公开(公告)日：2020-12-01
申请号：US16375572
申请日：2019-04-04
Applicant: Intel Corporation
Inventor： Roee Eitan , Ahmad B. Khairi , Yosi Sanhedrai , Ram Livne , Ilya Kraimer , Hen Sallem , Idan Lotan , Ariel Cohen , Dror Lazar
Abstract: A comparator is described. The comparator includes a differential pair having first and second transistors to respectively receive first and second input signals. The comparator also includes a current sink or source transistor coupled to respective source nodes of the first and second transistors. The current sink or source transistor is coupled to receive a fixed bias to keep the current sink transistor active so that large voltage changes on the source nodes is avoided. The comparator circuit includes a latch circuit coupled to respective drain nodes of the first and second transistors. The latch circuit is to reach a final state to present the comparator's output signal. The comparator includes a first switch circuit coupled between the first transistor's drain node and the latch circuit, and a second switch circuit coupled between the second transistor's drain node and the latch circuit. The first and second switch circuits to allow the first and second transistors' respective drain node voltage and source node voltage to enter and exit the comparator's comparison state at a same voltage.
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3.发明授权公开(公告)号：US10340938B1
公开(公告)日：2019-07-02
申请号：US15961460
申请日：2018-04-24
Applicant: Intel Corporation
Inventor： Roee Eitan , Ram Livne , Ahmad Khairi , Yoel Krupnik , Ariel Cohen
Abstract: An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.
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4.发明申请公开(公告)号：US20190326922A1
公开(公告)日：2019-10-24
申请号：US16459421
申请日：2019-07-01
Applicant: Intel Corporation
Inventor： Roee Eitan , Ram Livne , Ahmad Khairi , Yoel Krupnik , Ariel Cohen
Abstract: An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.
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