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1.发明授权公开(公告)号：US10340938B1
公开(公告)日：2019-07-02
申请号：US15961460
申请日：2018-04-24
Applicant: Intel Corporation
Inventor： Roee Eitan , Ram Livne , Ahmad Khairi , Yoel Krupnik , Ariel Cohen
Abstract: An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.
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2.发明授权公开(公告)号：US10756747B2
公开(公告)日：2020-08-25
申请号：US16459421
申请日：2019-07-01
Applicant: Intel Corporation
Inventor： Roee Eitan , Ram Livne , Ahmad Khairi , Yoel Krupnik , Ariel Cohen
Abstract: An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.
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Patent Agency Ranking
公开(公告)号：US09973356B1
公开(公告)日：2018-05-15
申请号：US15475690
申请日：2017-03-31
Applicant: Intel Corporation
Inventor： Ram Livne , Ro'ee Eitan , Yoel Krupnik , Vladislav Tsirkin , Tomer Fael , Dror Lazar , Ariel Cohen , Alexander Pogrebinsky , Adee Ofir Ran
CPC classification number: H04L25/03057
Abstract: One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.
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公开(公告)号：US11705916B2
公开(公告)日：2023-07-18
申请号：US17717558
申请日：2022-04-11
Applicant: Intel Corporation
Inventor： Yitzhak Elhanan Schifmann , Yoel Krupnik , Ariel Cohen
CPC classification number: H03M1/121 , G11C27/02 , H03F3/213 , H03F3/68 , H03M1/1245 , H03M1/38 , H04B1/16 , H03F2200/129 , H03F2200/231 , H03F2200/267 , H03F2200/69
Abstract: Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.
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5.发明申请公开(公告)号：US20190326922A1
公开(公告)日：2019-10-24
申请号：US16459421
申请日：2019-07-01
Applicant: Intel Corporation
Inventor： Roee Eitan , Ram Livne , Ahmad Khairi , Yoel Krupnik , Ariel Cohen
Abstract: An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.
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公开(公告)号：US11329662B2
公开(公告)日：2022-05-10
申请号：US16985104
申请日：2020-08-04
Applicant: Intel Corporation
Inventor： Yitzhak Elhanan Schifmann , Yoel Krupnik , Ariel Cohen
Abstract: Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.
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公开(公告)号：US10742227B1
公开(公告)日：2020-08-11
申请号：US16285060
申请日：2019-02-25
Applicant: Intel Corporation
Inventor： Yitzhak Elhanan Schifmann , Yoel Krupnik , Ariel Cohen
Abstract: Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.
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