公开(公告)号：US20160179687A1

公开(公告)日：2016-06-23

申请号：US14579934

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： SANJAY KUMAR ,  RAJESH SANKARAN ,  SUBRAMANYA DULLOOR ,  SHENG LI

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/128 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F3/0671 ,  G06F11/00 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0862 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/1027 ,  G06F2212/1032 ,  G06F2212/6028 ,  G06F2212/621

Abstract: A processor includes a processing core to execute an application including instructions encoding a transaction with a persistent memory via a volatile cache that includes a cache line associated with the transaction, the cache line being associated with a cache line status, and a cache controller operatively coupled to the volatile cache, the cache controller, in response to detecting a failure event, to, in response to determining that the cache line status that the cache line is committed, evict contents of the cache line to the persistent memory, and in response to determining that the cache line status indicating that the cache line is uncommitted, discard the contents of the cache line.

Abstract translation: 处理器包括处理核心，用于执行包括通过包括与事务相关联的高速缓存行的易失性高速缓冲存储器与持久存储器进行交易的指令的应用，所述高速缓存行与高速缓存行状态相关联，高速缓存控制器可操作地耦合 响应于确定高速缓存行被提交的高速缓存行状态，缓存控制器响应于检测到故障事件，将高速缓存行的内容驱逐到永久存储器，并且响应于缓存行 确定指示高速缓存行未被提交的高速缓存行状态，丢弃高速缓存行的内容。

公开(公告)号：US20160364340A1

公开(公告)日：2016-12-15

申请号：US15246811

申请日：2016-08-25

Applicant: Intel Corporation

Inventor： SANJAY KUMAR ,  RAJESH SANKARAN ,  SUBRAMANYA DULLOOR ,  SHENG LI

IPC: G06F12/128 ,  G06F3/06 ,  G06F12/0808

CPC classification number: G06F12/128 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F3/0671 ,  G06F11/00 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0862 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/1027 ,  G06F2212/1032 ,  G06F2212/6028 ,  G06F2212/621

Abstract: A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a near memory cache, wherein the near memory cache comprises a cache line comprising an identifier associated with the transaction and a status flag indicating whether the cache line is committed or uncommitted, and a cache controller operatively coupled to the near memory cache to determine, based on the status flag, what operation is to be performed with respect to contents of the cache line.

Abstract translation: 处理器包括处理核心，用于执行包括经由近程存储器高速缓冲存储器与持久存储器编码事务的指令的应用，其中所述近似存储器高速缓存包括包含与所述事务相关联的标识符的高速缓存行和指示所述高速缓存行 被提交或未提交，以及可操作地耦合到近存储器高速缓存的高速缓存控制器，以基于状态标志来确定要针对高速缓存行的内容执行什么操作。