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    PARALLEL COMPUTATION TECHNIQUES FOR ACCELERATED CRYPTOGRAPHIC CAPABILITIES
    2.
    发明申请
    PARALLEL COMPUTATION TECHNIQUES FOR ACCELERATED CRYPTOGRAPHIC CAPABILITIES 审中-公开

    公开(公告)号：US20180097625A1

    公开(公告)日：2018-04-05

    申请号：US15283323

    申请日：2016-10-01

    Applicant: INTEL CORPORATION

    Inventor： SUDHIR K. SATPATHY ,  RAGHAVAN KUMAR ,  SANU K. MATHEW ,  VIKRAM B. SURESH

    IPC: H04L9/30 ,  G09C1/00 ,  G06F7/72

    CPC classification number: H04L9/302 ,  G06F7/728 ,  G09C1/00 ,  H04L2209/125

    Abstract: Computing devices and techniques for performing modular exponentiation for a data encryption process are described. In one embodiment, for example, an apparatus may include at least one memory logic for an encryption unit to perform encryption according to RSA encryption using a parallel reduction multiplier (PRM) MM process, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one wireless transmitter, the logic to precompute a reduction coefficient, determine an operand product and a reduction product in parallel, the reduction product based on the reduction coefficient, and generate a MM result for the PRM MM process based on the operand product and the reduction product. Other embodiments are described and claimed.

    THRESHOLD FILTERING OF COMPRESSED DOMAIN DATA USING STEERING VECTOR
    3.
    发明申请
    THRESHOLD FILTERING OF COMPRESSED DOMAIN DATA USING STEERING VECTOR 有权
    使用转向矢量对压缩域数据进行阈值滤波

    公开(公告)号：US20160219295A1

    公开(公告)日：2016-07-28

    申请号：US14607113

    申请日：2015-01-28

    Applicant: Intel Corporation

    Inventor： SUDHIR K. SATPATHY ,  SANU K. MATHEW ,  RAM K. KRISHNAMURTHY

    IPC: H04N19/48 ,  G06T7/00 ,  H04N19/85 ,  G06F7/24

    CPC classification number: G06F7/533 ,  G06F7/24 ,  G06F7/5443 ,  G06T7/74 ,  G06T7/97 ,  H04N19/48 ,  H04N19/85

    Abstract: In an embodiment, a processor includes a compression domain threshold filter coupled to a plurality of cores. The compression domain threshold filter is to: receive a sample vector of compressed data to be filtered; calculate, based at least on a first subset of the elements of the sample vector, an estimated upper bound value of a dot product of the sample vector and a steering vector; determine whether the estimated upper bound value of the dot product satisfies a filter threshold value; and in response to a determination that the estimated upper bound value of the dot product does not satisfy the filter threshold value, discard the sample vector without completion of a calculation of the dot product of the sample vector and the steering vector. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括耦合到多个核的压缩域阈值滤波器。 压缩域阈值滤波器是：接收要滤波的压缩数据的采样向量; 至少基于样本矢量的元素的第一子集计算样本矢量和导向矢量的点积的估计上限值; 确定点积的估计上限值是否满足滤波器阈值; 并且响应于确定点积的估计上限值不满足滤波器阈值，而不完成样本矢量和导向矢量的点乘积的计算而丢弃样本矢量。 描述和要求保护其他实施例。

    TECHNIQUES FOR SECURE MESSAGE AUTHENTICATION WITH UNIFIED HARDWARE ACCELERATION
    4.
    发明申请
    TECHNIQUES FOR SECURE MESSAGE AUTHENTICATION WITH UNIFIED HARDWARE ACCELERATION 审中-公开

    公开(公告)号：US20180183577A1

    公开(公告)日：2018-06-28

    申请号：US15393196

    申请日：2016-12-28

    Applicant: INTEL CORPORATION

    Inventor： VIKRAM B. SURESH ,  KIRK S. YAP ,  SANU K. MATHEW ,  SUDHIR K. SATPATHY

    IPC: H04L9/06 ,  H04L9/32

    CPC classification number: H04L9/0643 ,  G09C1/00 ,  H04L2209/125

    Abstract: Techniques and computing devices for secure message authentication and, more specifically, but not exclusively, to techniques for unified hardware acceleration of hashing functions, such as SHA-1 and SHA-256 are described. In one embodiment, for example, an apparatus for hardware accelerated hashing in a computer system mat include at least one memory and at least one processor. The apparatus may further include logic comprising at least one adding circuit shared between a first hash function and a second hash function, the logic to perform hardware accelerated hashing of an input message stored in the at least one memory. At least a portion of the logic may be comprised in hardware and executed by the processor to receive the input message to be hashed using the first hash function, perform message expansion of the input message per requirements of the first hash function, perform hashing of the expanded input message over at least four computation rounds, perform, in each of a first, second, and third computation round, more than a single round of computation for the first hash function, and generate a message digest for the input message based upon the first hash function. Other embodiments are described and claimed.

    THRESHOLD FILTERING OF COMPRESSED DOMAIN DATA USING STEERING VECTOR
    5.
    发明申请
    THRESHOLD FILTERING OF COMPRESSED DOMAIN DATA USING STEERING VECTOR 审中-公开
    使用转向矢量对压缩域数据进行阈值滤波

    公开(公告)号：US20170039034A1

    公开(公告)日：2017-02-09

    申请号：US15296139

    申请日：2016-10-18

    Applicant: Intel Corporation

    Inventor： SUDHIR K. SATPATHY ,  SANU K. MATHEW ,  RAM K. KRISHNAMURTHY

    IPC: G06F7/533

    CPC classification number: G06F7/533 ,  G06F7/24 ,  G06F7/5443 ,  G06T7/74 ,  G06T7/97 ,  H04N19/48 ,  H04N19/85

    Abstract: In an embodiment, a processor includes a compression domain threshold filter coupled to a plurality of cores. The compression domain threshold filter is to: receive a sample vector of compressed data to be filtered; calculate, based at least on a first subset of the elements of the sample vector, an estimated upper bound value of a dot product of the sample vector and a steering vector; determine whether the estimated upper bound value of the dot product satisfies a filter threshold value; and in response to a determination that the estimated upper bound value of the dot product does not satisfy the filter threshold value, discard the sample vector without completion of a calculation of the dot product of the sample vector and the steering vector. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括耦合到多个核的压缩域阈值滤波器。 压缩域阈值滤波器是：接收要滤波的压缩数据的采样向量; 至少基于样本矢量的元素的第一子集计算样本矢量和导向矢量的点积的估计上限值; 确定点积的估计上限值是否满足滤波器阈值; 并且响应于确定点积的估计上限值不满足滤波器阈值，而不完成样本矢量和导向矢量的点乘积的计算而丢弃样本矢量。 描述和要求保护其他实施例。

    TECHNIQUES TO POWER ENCRYPTION CIRCUITRY
    6.
    发明申请
    TECHNIQUES TO POWER ENCRYPTION CIRCUITRY 审中-公开

    公开(公告)号：US20190007223A1

    公开(公告)日：2019-01-03

    申请号：US15640469

    申请日：2017-07-01

    Applicant: INTEL CORPORATION

    Inventor： VAIBHAV VAIDYA ,  SANU K. MATHEW ,  SUDHIR K. SATPATHY ,  RAGHAVAN KUMAR

    IPC: H04L9/38 ,  H04L9/06

    Abstract: Various embodiments are generally directed to techniques to power encryption circuitry, such as with a power converter, for instance. Some embodiments are particularly directed to a power converter that utilizes one or more capacitors to power encryption circuitry while masking the power signature of the encryption circuitry. In one or more embodiments, for example, a power converter may charge a capacitor with a power source of a computing platform, and then power encryption circuitry with the capacitor to perform a first portion of an encryption operation. In one or more such embodiments, the power converter may recharge the capacitor with the power source after completion of the first portion of the encryption operation, and perform a second portion of the encryption operation.

    METHOD AND APPARATUS FOR SPECULATIVE DECOMPRESSION
    9.
    发明申请
    METHOD AND APPARATUS FOR SPECULATIVE DECOMPRESSION 有权
    用于测量分解的方法和装置

    公开(公告)号：US20160321076A1

    公开(公告)日：2016-11-03

    申请号：US14698486

    申请日：2015-04-28

    Applicant: Intel Corporation

    Inventor： SUDHIR K. SATPATHY ,  SANU K. MATHEW ,  VINODH GOPAL ,  JAMES D. GUILFORD

    IPC: G06F9/30

    CPC classification number: G06F9/30185 ,  G06F9/30021 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30156 ,  G06F9/3016 ,  H03M7/4037 ,  H03M7/6005 ,  H03M7/6023

    Abstract: An apparatus and method for performing parallel decoding of prefix codes such as Huffman codes. For example, one embodiment of an apparatus comprises: a first decompression module to perform a non-speculative decompression of a first portion of a prefix code payload comprising a first plurality of symbols; and a second decompression module to perform speculative decompression of a second portion of the prefix code payload comprising a second plurality of symbols concurrently with the non-speculative decompression performed by the first compression module.

    Abstract translation: 一种用于执行诸如霍夫曼码之类的前缀码的并行解码的装置和方法。 例如，装置的一个实施例包括：第一解压缩模块，用于执行包括第一多个符号的前缀码有效载荷的第一部分的非推测解压缩; 以及第二解压缩模块，用于执行与由第一压缩模块执行的非推测性解压缩同时地包括第二多个符号的前缀码有效载荷的第二部分的推测性解压缩。

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