公开(公告)号：US20200212039A1

公开(公告)日：2020-07-02

申请号：US16812726

申请日：2020-03-09

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Salman LATIF ,  Chanaka D. MUNASINGHE

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/225 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

公开(公告)号：US20190006362A1

公开(公告)日：2019-01-03

申请号：US16103430

申请日：2018-08-14

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Salman LATIF ,  Chanaka D. MUNASINGHE

IPC: H01L27/092 ,  H01L29/08 ,  H01L21/225 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/31051 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66803

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

公开(公告)号：US20210175233A1

公开(公告)日：2021-06-10

申请号：US17183214

申请日：2021-02-23

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Salman LATIF ,  Chanaka D. MUNASINGHE

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/225 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

公开(公告)号：US20190341383A1

公开(公告)日：2019-11-07

申请号：US16510688

申请日：2019-07-12

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Salman LATIF ,  Chanaka D. MUNASINGHE

IPC: H01L27/092 ,  H01L29/08 ,  H01L21/225 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.