公开(公告)号：US20230096154A1

公开(公告)日：2023-03-30

申请号：US17484323

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Siddhartha Selvaraj ,  Pannerkumar Rajagopal ,  Devanathan Kannan

IPC: G06F1/26 ,  G06F1/18 ,  H02J7/00

Abstract: A chassis structure of an apparatus contains a battery. Charger circuitry is operable to provide charge to the battery. Discharge circuitry is operable to receive charge from the battery. Switch circuitry is coupled between the battery and each of the charger circuitry, the discharge circuitry, and a load. A connector at an exterior surface of the chassis couples the apparatus to a power supply. The switch circuitry is coupled to the connector via the charger circuitry. A first control activable at the exterior surface of the chassis structure is operable to generate, in response to being activated, a first control signal to request a first switch state wherein the battery is electrically coupled to the discharge circuitry. A controller circuit coupled to receive the first control signal from the first control and, based on the first control signal, to operate the switch circuitry to provide the first switch state.

公开(公告)号：US20230342234A1

公开(公告)日：2023-10-26

申请号：US17724811

申请日：2022-04-20

Applicant: Intel Corporation

Inventor： Pannerkumar Rajagopal ,  Santhosh Raghuram Krishnaswamy ,  Siddhartha Selvaraj ,  Anshul Soni ,  Toby Zimmerman

IPC: G06F11/07 ,  G06F9/4401

CPC classification number: G06F11/0766 ,  G06F9/4406 ,  G06F11/0721

Abstract: The technology describe herein includes upon entering a mode of a processor that is not visible to an operating system (OS), setting a flag indicating entry into the mode and saving an identifier (ID) of an error causing entry into the mode; and responsive to a system reset initiation while in the mode, booting a basic input/output system (BIOS), creating an error record to be accessible to the OS after booting, the error record including the flag and the error ID, and booting the OS.

公开(公告)号：US20220215099A1

公开(公告)日：2022-07-07

申请号：US17705747

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Sriram Ranganathan ,  Pannerkumar Rajagopal ,  Saravanakumar Ulaganathan ,  Siddhartha Selvaraj ,  Radhakrishna Pai

IPC: G06F21/57 ,  G06F15/78

Abstract: The disclosure generally relates method, system and apparatus to prevent denial of service (DOS) attacks on PCIe based computing devices. In an exemplary embodiment, an independent register is used in combination with a filter driver and additional logic to form an integrity check for power down instructions. An exemplary system includes a register circuitry corresponding to the IP device, the register circuitry having a designated storage bit to indicate an unlocked state of the register; a filter driver to receive a first power state transition request when the IP device is idle after a predetermined period, the power state transition request defining a timeout period; a controller to change the power state of the IP device to the unlock state; a decision logic to receive and authenticate a second power state transition request in response to validation of register circuitry being unlocked.