公开(公告)号：US20190189226A1

公开(公告)日：2019-06-20

申请号：US15845683

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Amit Kumar SRIVASTAVA ,  Sriram BALASUBRAHMANYAM

IPC: G11C16/32

CPC classification number: G11C16/32 ,  G11C7/22

Abstract: An apparatus is provided which comprises: a buffer to receive first data from a host, and output the first data with configurable delay; and one or more circuitries to: compare the first data from the host with second data that is accessible to the apparatus, wherein the second data is substantially a copy of the first data, and calibrate the delay of the buffer, based at least in part on the comparison of the first data and the second data.

公开(公告)号：US20190252033A1

公开(公告)日：2019-08-15

申请号：US16168809

申请日：2018-10-23

Applicant: Intel Corporation

Inventor： Varsha REGULAPATI ,  Heonwook KIM ,  Aliasgar S. MADRASWALA ,  Naga Kiranmayee UPADHYAYULA ,  Purval S. SULE ,  Jong Tai PARK ,  Sriram BALASUBRAHMANYAM ,  Manjiri M. KATMORE

IPC: G11C29/02 ,  G11C16/32 ,  G11C16/04 ,  G06F13/16 ,  G06F12/02

CPC classification number: G11C29/023 ,  G06F12/0246 ,  G06F13/1668 ,  G11C16/0483 ,  G11C16/32 ,  G11C29/028

Abstract: In connection with data pin timing calibration with a strobe signal, examples provide for determination of pass/fail status of a pin from multiple pass/fail results in a single operation. Determination of pass/fail results for multiple pins based on multiple applied trim offsets can be made in parallel. Accordingly, a time to determine pass/fail results from multiple trim values for a pin can be reduced, which can enable faster power-up of NAND flash devices.