公开(公告)号：US20190004887A1

公开(公告)日：2019-01-03

申请号：US15640487

申请日：2017-07-01

Applicant: INTEL CORPORATION

Inventor： Stalinselvaraj Jeyasingh ,  Subhankar Panda ,  David A. Locklear ,  Steven A. Filary ,  Christopher J. Stedman ,  Carlos Vallin

IPC: G06F11/07 ,  G06F11/14

Abstract: Techniques and apparatus for remotely accessing debugging resources of a target system are described. A target system including physical compute resources, such as, processors and a chipset can be coupled to a controller remotely accessible over a network. The controller can be arranged to facilitate remote access to debug resources of the physical compute resources. The controller can be coupled to debug pin, such as, those of a debug port and arranged to assert control signals on the pins to access debug resources. The controller can also be arranged to exchange information elements with a remote debug host to include indication of debug operations and/or debug results.

公开(公告)号：US10102380B2

公开(公告)日：2018-10-16

申请号：US13802272

申请日：2013-03-13

Applicant: INTEL CORPORATION

Inventor： Francis X. McKeen ,  Carlos V. Rozas ,  Uday R. Savagaonkar ,  Simon P. Johnson ,  Vincent Scarlata ,  Michael A. Goldsmith ,  Ernie Brickell ,  Jiang Tao Li ,  Howard C. Herbert ,  Prashant Dewan ,  Stephen J. Tolopka ,  Gilbert Neiger ,  David Durham ,  Gary Graunke ,  Bernard Lint ,  Don A. Van Dyke ,  Joseph Cihula ,  Stalinselvaraj Jeyasingh ,  Stephen R. Van Doren ,  Dion Rodgers ,  John Garney ,  Asher Altman

IPC: G06F21/60 ,  G06F21/72 ,  G06F21/53

Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.

公开(公告)号：US20170177377A1

公开(公告)日：2017-06-22

申请号：US14976990

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Arumugam Thiyagarajah ,  Gaurav Khanna ,  Stalinselvaraj Jeyasingh ,  Sohil Mehta ,  Mukesh J. Jagasia

IPC: G06F9/44

CPC classification number: G06F9/4406 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/45558 ,  G06F2009/45575 ,  G06F2009/45579

Abstract: Apparatuses, methods and storage medium associated with virtual machine application processor startup, are disclosed herein. In embodiments, an apparatus for computing may include a plurality of processor cores; and a plurality of OS modules of an OS. The OS modules may include a BSP module and an AP module. The BSP module may be configured to write into a storage area a start state of an AP of a VM, while the VM is being started up; and the AP module may be configured to start the AP at the start state, directly in a protected mode of execution without first going through a real mode of execution. Other embodiments may be described and/or claimed.

公开(公告)号：US09898307B2

公开(公告)日：2018-02-20

申请号：US14976990

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Arumugam Thiyagarajah ,  Gaurav Khanna ,  Stalinselvaraj Jeyasingh ,  Sohil Mehta ,  Mukesh J. Jagasia

IPC: G06F9/00 ,  G06F9/24 ,  G06F15/177 ,  G06F9/44

CPC classification number: G06F9/4406 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/45558 ,  G06F2009/45575 ,  G06F2009/45579

Abstract: Apparatuses, methods and storage medium associated with virtual machine application processor startup, are disclosed herein. In embodiments, an apparatus for computing may include a plurality of processor cores; and a plurality of OS modules of an OS. The OS modules may include a BSP module and an AP module. The BSP module may be configured to write into a storage area a start state of an AP of a VM, while the VM is being started up; and the AP module may be configured to start the AP at the start state, directly in a protected mode of execution without first going through a real mode of execution. Other embodiments may be described and/or claimed.

公开(公告)号：US11573845B2

公开(公告)日：2023-02-07

申请号：US17217545

申请日：2021-03-30

Applicant: INTEL CORPORATION

Inventor： Stalinselvaraj Jeyasingh ,  Subhankar Panda ,  David A. Locklear ,  Steven A. Filary ,  Christopher J. Stedman ,  Carlos Vallin

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/14 ,  G06F11/27 ,  G06F11/22

Abstract: Techniques and apparatus for remotely accessing debugging resources of a target system are described. A target system including physical compute resources, such as, processors and a chipset can be coupled to a controller remotely accessible over a network. The controller can be arranged to facilitate remote access to debug resources of the physical compute resources. The controller can be coupled to debug pin, such as, those of a debug port and arranged to assert control signals on the pins to access debug resources. The controller can also be arranged to exchange information elements with a remote debug host to include indication of debug operations and/or debug results.

公开(公告)号：US20210216392A1

公开(公告)日：2021-07-15

申请号：US17217545

申请日：2021-03-30

Applicant: INTEL CORPORATION

Inventor： Stalinselvaraj Jeyasingh ,  Subhankar Panda ,  David A. Locklear ,  Steven A. Filary ,  Christopher J. Stedman ,  Carlos Vallin

IPC: G06F11/07 ,  G06F11/14 ,  G06F11/27 ,  G06F11/22

Abstract: Techniques and apparatus for remotely accessing debugging resources of a target system are described. A target system including physical compute resources, such as, processors and a chipset can be coupled to a controller remotely accessible over a network. The controller can be arranged to facilitate remote access to debug resources of the physical compute resources. The controller can be coupled to debug pin, such as, those of a debug port and arranged to assert control signals on the pins to access debug resources. The controller can also be arranged to exchange information elements with a remote debug host to include indication of debug operations and/or debug results.

公开(公告)号：US11016833B2

公开(公告)日：2021-05-25

申请号：US15640487

申请日：2017-07-01

Applicant: INTEL CORPORATION

Inventor： Stalinselvaraj Jeyasingh ,  Subhankar Panda ,  David A. Locklear ,  Steven A. Filary ,  Christopher J. Stedman ,  Carlos Vallin

IPC: G06F11/07 ,  G06F11/14 ,  G06F11/27 ,  G06F11/22

Abstract: Techniques and apparatus for remotely accessing debugging resources of a target system are described. A target system including physical compute resources, such as, processors and a chipset can be coupled to a controller remotely accessible over a network. The controller can be arranged to facilitate remote access to debug resources of the physical compute resources. The controller can be coupled to debug pin, such as, those of a debug port and arranged to assert control signals on the pins to access debug resources. The controller can also be arranged to exchange information elements with a remote debug host to include indication of debug operations and/or debug results.

公开(公告)号：US10885202B2

公开(公告)日：2021-01-05

申请号：US16123593

申请日：2018-09-06

Applicant: Intel Corporation

Inventor： Francis X. McKeen ,  Carlos V. Rozas ,  Uday R. Savagaonkar ,  Simon P. Johnson ,  Vincent Scarlata ,  Michael A. Goldsmith ,  Ernie Brickell ,  Jiang Tao Li ,  Howard C. Herbert ,  Prashant Dewan ,  Stephen J. Tolopka ,  Gilbert Neiger ,  David Durham ,  Gary Graunke ,  Bernard Lint ,  Don A. Van Dyke ,  Joseph Cihula ,  Stalinselvaraj Jeyasingh ,  Stephen R. Van Doren ,  Dion Rodgers ,  John Garney ,  Asher Altman

IPC: G06F21/60 ,  G06F21/72 ,  G06F21/53

Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.

公开(公告)号：US09971615B2

公开(公告)日：2018-05-15

申请号：US13836628

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Gilbert Neiger ,  Richard Uhlig ,  Xiang Zou ,  Lawrence Smith, III ,  Scott Rodgers

IPC: G06F9/46 ,  G06F9/455

CPC classification number: G06F9/45533 ,  G06F9/45558 ,  G06F2009/45583

Abstract: In one embodiment, a predefined behavior of a virtual machine monitor (VMM) with respect to one or more virtual machines (VMs) is identified, and processor-managed resources associated with the one or more VMs are utilized based on the predefined behavior of the VMM.

公开(公告)号：US08751752B2

公开(公告)日：2014-06-10

申请号：US13837648

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Eric C. Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Michael A. Kozuch ,  Gilbert Neiger ,  Richard Uhlig

IPC: G06F12/08

CPC classification number: G06F12/1027 ,  G06F9/30076 ,  G06F12/1036 ,  G06F2212/151

Abstract: One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.

Abstract translation: 本发明的一个实施例是使翻译后备缓冲器（TLB）中的条目无效的技术。 处理器中的TLB具有多个TLB条目。 当执行无效操作时，每个TLB条目与虚拟机扩展（VMX）标签字相关联，指示相关联的TLB条目是否根据处理器模式而无效。 处理器模式是虚拟机（VM）中的执行之一，而不是虚拟机中的执行。 无效操作属于一个无效的无效操作集合，它由（1）可能为空的操作集合组合，使一组可变数量的TLB条目无效，（2）一组可能的空白操作，使一个TLB无效 条目，（3）使多个TLB条目无效的可能的一组操作，（4）启用和禁用虚拟存储器的使用的可能的一组可能的空操作，以及（5）配置物理的可能的一组操作 地址大小，页面大小或其他虚拟内存系统行为，以改变物理机器解释TLB条目的方式。