公开(公告)号：US20250112191A1

公开(公告)日：2025-04-03

申请号：US18374920

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Thomas WAGNER ,  Pouya TALEBBEYDOKHTI ,  Stephan STOECKL ,  Lizabeth KESER

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/48 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package comprises an interposer with at least one open area through the interposer. A first die is connected to a first side of the interposer. A second die is connected to a second side of the interposer. At least one metal pillar is connected to the first die that extends through the open area of the interposer and connects to the second die to provide a direct die-to-die connection through the interposer.

公开(公告)号：US20250112202A1

公开(公告)日：2025-04-03

申请号：US18374948

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Abdallah BACHA ,  Cindy MUIR ,  Mohan Prashanth JAVARE GOWDA ,  Stephan STOECKL ,  Thomas WAGNER ,  Wolfgang MOLZER

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H01L25/10 ,  H10B80/00

Abstract: Embodiments herein relate to systems, apparatuses, or processes for packages that include substrates that include one or more die in a cavity within the substrate, where sides and a bottom of the cavity are lined with a heat spreader, or TIM, material that is thermally coupled to a side of the substrate using thermally conductive vias. In embodiments, thermally conductive vias may be thermally coupled with the heat spreader at the side of the substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20250112139A1

公开(公告)日：2025-04-03

申请号：US18374954

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Abdallah BACHA ,  Thomas WAGNER ,  Cindy MUIR ,  Mohan Prashanth JAVARE GOWDA ,  Stephan STOECKL ,  Wolfgang MOLZER

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065

Abstract: Embodiments herein relate to systems, apparatuses, or processes for forming a die that has active circuitry within the die and also one or more vias that extend through the die that are electrically isolated from the active circuitry. In embodiments, the active circuitry may be within a region within a die, for example in the center of the die, and the vias may be in an extended area around the active circuitry of the die. In embodiments, an existing die may be provided, and an extended area may be formed on the existing die into which the vias may be placed. Other embodiments may be described and/or claimed.

公开(公告)号：US20240332251A1

公开(公告)日：2024-10-03

申请号：US18129878

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Min Suet LIM ,  Kavitha NAGARAJAN ,  Stephan STOECKL ,  Eng Huat GOH

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/3511 ,  H10B80/00

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, a plurality of first dies are coupled to the first surface of the substrate, and a bump field is on the second surface of the substrate. In an embodiment, the bump field comprises a voided region towards a center of the substrate. In an embodiment, a second die is coupled to the second surface of the substrate, where the second die is provided in the voided region.

公开(公告)号：US20230317536A1

公开(公告)日：2023-10-05

申请号：US17707536

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Georg SEIDEMANN ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Stephan STOECKL

IPC: H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/3107 ,  H01L23/5381 ,  H01L25/0655 ,  H01L21/56

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes related to packages that are fully or partially encapsulated in a mold material, with one or more grooves in the mold material to reduce failure in the package during operation. In embodiments, the grooves will allow greater flexibility within the body of the package as it experiences thermo-mechanical stress during operation and will reduce stresses that may be placed on internal components such as chips or bridges in the package, as well as stresses that may be placed on interconnects of the package that are coupled to a substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20210193594A1

公开(公告)日：2021-06-24

申请号：US16721095

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Stephan STOECKL ,  Wolfgang MOLZER ,  Georg SEIDEMANN ,  Bernd WAIDHAS

IPC: H01L23/58 ,  H01L23/31 ,  H01L49/02 ,  H01L21/683 ,  H01L21/56

Abstract: Embodiments disclosed herein include semiconductor packages. In a particular embodiment, the semiconductor package is a wafer level chip scale package (WLCSP). In an embodiment, the WLCSP comprises a die. In an embodiment, the die comprises an active surface and a backside surface. The die has a first coefficient of thermal expansion (CTE). In an embodiment, the WLCSP further comprises a channel into the die. In an embodiment, the channel is filled with a stress relief material, where the stress relief material has a second CTE that is greater than the first CTE.