公开(公告)号：US10860524B2

公开(公告)日：2020-12-08

申请号：US14722821

申请日：2015-05-27

Applicant: Intel Corporation

Inventor： Dennis C. Abts ,  Robert Alverson ,  Edwin Froese ,  Howard Pritchard ,  Steven L. Scott

IPC: G06F15/167 ,  G06F12/0813 ,  G06F12/1009 ,  H04L29/08 ,  G06F9/38 ,  G06F13/40

Abstract: A multiprocessor computer system comprises a first node operable to access memory local to a remote node by receiving a virtual memory address from a requesting entity in node logic in the first node. The first node creates a network address from the virtual address received in the node logic, where the network address is in a larger address space than the virtual memory address, and sends a fast memory access request from the first node to a network node identified in the network address.

公开(公告)号：US10153985B2

公开(公告)日：2018-12-11

申请号：US15435952

申请日：2017-02-17

Applicant: Intel Corporation ,  The Board of Trustees of the Leland Stanford Junior University

Inventor： John Kim ,  Dennis C. Abts ,  Steven L. Scott ,  William J. Dally

IPC: H04L12/933 ,  H04L12/931 ,  G06F15/173 ,  H04L12/775 ,  G06F9/455 ,  G06F13/40 ,  G06F13/42 ,  H04L12/703

Abstract: A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such that each group is connected to each other group via at least one direct connection.

公开(公告)号：US09614786B2

公开(公告)日：2017-04-04

申请号：US14583588

申请日：2014-12-27

Applicant: Intel Corporation ,  The Board of Trustees of the Leland Stanford Junior University

Inventor： John Kim ,  Dennis C. Abts ,  Steven L. Scott ,  William J. Dally

IPC: G06F13/42 ,  H04L12/933 ,  H04L12/931 ,  G06F15/173 ,  H04L12/775 ,  G06F9/455 ,  G06F13/40 ,  H04L12/703

CPC classification number: H04L49/15 ,  G06F9/45533 ,  G06F13/4027 ,  G06F13/4221 ,  G06F15/17375 ,  H04L45/28 ,  H04L45/58 ,  H04L49/1515 ,  H04L49/70

Abstract: A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such that each group is connected to each other group via at least one direct connection.

公开(公告)号：US09537772B2

公开(公告)日：2017-01-03

申请号：US14310832

申请日：2014-06-20

Applicant: Intel Corporation

Inventor： Steven L. Scott ,  Gregory Hubbard ,  Dennis C. Abts

IPC: H04L12/28 ,  H04L12/743 ,  G06F15/173 ,  H04L12/701 ,  H04L12/703 ,  H04L12/721 ,  H04L12/741 ,  H04L12/933

CPC classification number: H04L45/7453 ,  G06F15/17362 ,  H04L45/00 ,  H04L45/28 ,  H04L45/566 ,  H04L45/745 ,  H04L49/15

Abstract: A system and method for routing in a high-radix network. A packet is received and examined to determine if the packet can be routed adaptively. If the packet can be routed adaptively, the packet is routed adaptively, wherein routing adaptively includes selecting a column, computing a column mask, routing the packet to the column; and selecting an output port as a function of the column mask. If the packet can be routed deterministically, routing deterministically, wherein routing deterministically includes accessing a routing table to obtain an output port and routing the packet to the output port from the routing table.

Abstract translation: 用于在高基数网络中路由的系统和方法。 接收并检查分组以确定分组是否可以自适应路由。 如果分组可以自适应地路由，则分组自适应路由，其中​​路由自适应地包括选择列，计算列掩码，将分组路由到列; 并根据列屏蔽选择输出端口。 如果分组可以确定地路由路由，确定性地进行路由，其中​​路由确定性地包括访问路由表以获得输出端口并且将路由从路由表路由到输出端口。

公开(公告)号：US20170353401A1

公开(公告)日：2017-12-07

申请号：US15435952

申请日：2017-02-17

Applicant: Intel Corporation ,  The Board of Trustees of the Leland Stanford Junior University

Inventor： John Kim ,  Dennis C. Abts ,  Steven L. Scott ,  William J. Dally

IPC: H04L12/933 ,  H04L12/931 ,  G06F9/455 ,  G06F15/173 ,  G06F13/42 ,  G06F13/40 ,  H04L12/775 ,  H04L12/703

CPC classification number: H04L49/15 ,  G06F9/45533 ,  G06F13/4027 ,  G06F13/4221 ,  G06F15/17375 ,  H04L45/28 ,  H04L45/58 ,  H04L49/1515 ,  H04L49/70

Abstract: A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such that each group is connected to each other group via at least one direct connection.

公开(公告)号：US20150378961A1

公开(公告)日：2015-12-31

申请号：US14722821

申请日：2015-05-27

Applicant: Intel Corporation

Inventor： Dennis C. Abts ,  Robert Alverson ,  Edwin Froese ,  Howard Pritchard ,  Steven L. Scott

IPC: G06F15/167 ,  G06F12/10

CPC classification number: G06F15/167 ,  G06F9/3834 ,  G06F12/0813 ,  G06F12/1009 ,  G06F12/109 ,  G06F13/4009 ,  G06F2212/163 ,  H04L67/00

Abstract: A multiprocessor computer system comprises a first node operable to access memory local to a remote node by receiving a virtual memory address from a requesting entity in node logic in the first node. The first node creates a network address from the virtual address received in the node logic, where the network address is in a larger address space than the virtual memory address, and sends a fast memory access request from the first node to a network node identified in the network address.

Abstract translation: 多处理器计算机系统包括第一节点，用于通过从第一节点中的节点逻辑中的请求实体接收虚拟存储器地址来访问远程节点本地的存储器。 第一节点从节点逻辑中接收的虚拟地址创建网络地址，其中网络地址处于比虚拟存储器地址更大的地址空间中，并且将快速存储器访问请求从第一节点发送到在 网络地址。