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公开(公告)号：US08683240B2
公开(公告)日：2014-03-25
申请号：US13780038
申请日：2013-02-28
Applicant: Intel Corporation
Inventor： James S. Burns , Baskaran Ganesan , Russell J. Fenger , Devadatta V. Bodas , Sundaravarathan R. Iyengar , Feranak Nelson , John M. Powell, Jr. , Suresh Sugumar
CPC classification number: G06F1/3287 , G06F1/26 , G06F1/329 , G06F9/5094 , Y02D10/22 , Y02D10/24
Abstract: In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器具有多个核来执行线程。 处理器还包括功率控制逻辑，用于基于存储核心功率计数的计数器的阈值和识别至少一个线程的turbo模式请求的性能组合之间的比较来进入turbo模式。 以这种方式，可以在提供高功率效率的处理器的利用水平上输入turbo模式。 描述和要求保护其他实施例。
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公开(公告)号：US08904205B2
公开(公告)日：2014-12-02
申请号：US14171148
申请日：2014-02-03
Applicant: Intel Corporation
Inventor： James S. Burns , Baskaran Ganesan , Russell J. Fenger , Devadatta V. Bodas , Sundaravarathan R. Iyengar , Feranak Nelson , John M. Powell, Jr. , Suresh Sugumar
CPC classification number: G06F1/3287 , G06F1/26 , G06F1/329 , G06F9/5094 , Y02D10/22 , Y02D10/24
Abstract: In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.
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