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公开(公告)号：US08892929B2
公开(公告)日：2014-11-18
申请号：US13780103
申请日：2013-02-28
Applicant: Intel Corporation
Inventor： Srikanth Balasubramanian , Tessil Thomas , Satish Shrimali , Baskaran Ganesan
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3237 , G06F1/324 , Y02D10/128 , Y02D50/20
Abstract: In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.
Abstract translation: 在一个实施例中，多核处理器包括多个核和一个非核，其中该无孔包括包含高速缓冲存储器，路由器和功率控制单元（PCU）的各种逻辑单元。 当多核处理器处于低功率状态时，PCU可以对逻辑单元和高速缓冲存储器中的至少一个进行时钟门控，从而降低动态功耗。
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公开(公告)号：US20170010991A1
公开(公告)日：2017-01-12
申请号：US15270151
申请日：2016-09-20
Applicant: Intel Corporation
Inventor： Mahesh Natu , Thanunathan Rangarajan , Gautam Doshi , Shamanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
IPC: G06F13/24 , G11C7/10 , G11C11/406
CPC classification number: G06F13/24 , G06F9/30101 , G06F9/3017 , G06F9/30189 , G06F9/3851 , G06F9/461 , G11C7/1072 , G11C11/40615
Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的体系结构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。
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3.发明授权Providing state storage in a processor for system management mode selectively enabled by register bit instead of external SMRAM 有权在处理器中提供状态存储器，用于通过寄存器位而不是外部SMRAM选择性地启用系统管理模式公开(公告)号：US09465647B2
公开(公告)日：2016-10-11
申请号：US14048451
申请日：2013-10-08
Applicant: INTEL CORPORATION
Inventor： Mahesh Natu , Thanunathan Rangarajan , Gautam Doshi , Shamanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
CPC classification number: G06F13/24 , G06F9/30101 , G06F9/3017 , G06F9/30189 , G06F9/3851 , G06F9/461 , G11C7/1072 , G11C11/40615
Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的架构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。
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公开(公告)号：US09405340B2
公开(公告)日：2016-08-02
申请号：US13928724
申请日：2013-06-27
Applicant: Intel Corporation
Inventor： Baskaran Ganesan , Eric Dehaemer , Vinod Ambrose , Harjinder Hullon , Joseph Doucette , Seow Fung Ooi , Min Huang , Zhiguo Wang , Yin-Lung Lu , William Johnson Bowhill
CPC classification number: G06F1/26 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating voltage of each core at each of a plurality of frequencies. Each cluster includes a unique set of cores and at least one cluster includes at least two of the cores. The processor also includes a power control unit (PCU) including frequency/voltage control logic, responsive to a frequency change request for a first core of a first cluster, to determine an operating voltage for the first core from a first cluster voltage-frequency (V-F) table associated with the first cluster. The first cluster V-F table uniquely specifies a corresponding operating voltage at each of a plurality of frequencies of operation of the cores of the first cluster. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括分组为多个群集的多个核心。 基于在多个频率中的每一个处的每个核心的对应的工作电压来形成簇。 每个集群包括唯一的一组核心，并且至少一个集群包括至少两个核心。 所述处理器还包括功率控制单元（PCU），其响应于对第一集群的第一核心的频率变化请求而包括频率/电压控制逻辑，以从第一集群电压 - 频率（ VF）表与第一个集群关联。 第一簇V-F表在第一簇的核的多个操作频率的每一个上唯一地指定对应的工作电压。 描述和要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US09405358B2
公开(公告)日：2016-08-02
申请号：US14515694
申请日：2014-10-16
Applicant: Intel Corporation
Inventor： Srikanth Balasubramanian , Tessil Thomas , Satish Shrimali , Baskaran Ganesan
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3237 , G06F1/324 , Y02D10/128 , Y02D50/20
Abstract: In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.
Abstract translation: 在一个实施例中，多核处理器包括多个核和一个非核，其中该无孔包括包含高速缓冲存储器，路由器和功率控制单元（PCU）的各种逻辑单元。 当多核处理器处于低功率状态时，PCU可以对逻辑单元和高速缓冲存储器中的至少一个进行时钟门控，从而降低动态功耗。
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公开(公告)号：US08904205B2
公开(公告)日：2014-12-02
申请号：US14171148
申请日：2014-02-03
Applicant: Intel Corporation
Inventor： James S. Burns , Baskaran Ganesan , Russell J. Fenger , Devadatta V. Bodas , Sundaravarathan R. Iyengar , Feranak Nelson , John M. Powell, Jr. , Suresh Sugumar
CPC classification number: G06F1/3287 , G06F1/26 , G06F1/329 , G06F9/5094 , Y02D10/22 , Y02D10/24
Abstract: In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.
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公开(公告)号：US10169268B2
公开(公告)日：2019-01-01
申请号：US15270151
申请日：2016-09-20
Applicant: Intel Corporation
Inventor： Mahesh Natu , Thanunathan Rangarajan , Gautam Doshi , Shamanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
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公开(公告)号：US20180143923A1
公开(公告)日：2018-05-24
申请号：US15873089
申请日：2018-01-17
Applicant: Intel Corporation
Inventor： Mahesh Natu , Thanunathan Rangarajan , Gautam Doshi , Shamanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
CPC classification number: G06F13/24 , G06F9/30101 , G06F9/3017 , G06F9/30189 , G06F9/3851 , G06F9/461 , G11C7/1072 , G11C11/40615
Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
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公开(公告)号：US08683240B2
公开(公告)日：2014-03-25
申请号：US13780038
申请日：2013-02-28
Applicant: Intel Corporation
Inventor： James S. Burns , Baskaran Ganesan , Russell J. Fenger , Devadatta V. Bodas , Sundaravarathan R. Iyengar , Feranak Nelson , John M. Powell, Jr. , Suresh Sugumar
CPC classification number: G06F1/3287 , G06F1/26 , G06F1/329 , G06F9/5094 , Y02D10/22 , Y02D10/24
Abstract: In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器具有多个核来执行线程。 处理器还包括功率控制逻辑，用于基于存储核心功率计数的计数器的阈值和识别至少一个线程的turbo模式请求的性能组合之间的比较来进入turbo模式。 以这种方式，可以在提供高功率效率的处理器的利用水平上输入turbo模式。 描述和要求保护其他实施例。
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