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公开(公告)号：US08683240B2
公开(公告)日：2014-03-25
申请号：US13780038
申请日：2013-02-28
申请人： Intel Corporation
发明人： James S. Burns , Baskaran Ganesan , Russell J. Fenger , Devadatta V. Bodas , Sundaravarathan R. Iyengar , Feranak Nelson , John M. Powell, Jr. , Suresh Sugumar
CPC分类号： G06F1/3287 , G06F1/26 , G06F1/329 , G06F9/5094 , Y02D10/22 , Y02D10/24
摘要： In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器具有多个核来执行线程。 处理器还包括功率控制逻辑，用于基于存储核心功率计数的计数器的阈值和识别至少一个线程的turbo模式请求的性能组合之间的比较来进入turbo模式。 以这种方式，可以在提供高功率效率的处理器的利用水平上输入turbo模式。 描述和要求保护其他实施例。
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公开(公告)号：US08904205B2
公开(公告)日：2014-12-02
申请号：US14171148
申请日：2014-02-03
申请人： Intel Corporation
发明人： James S. Burns , Baskaran Ganesan , Russell J. Fenger , Devadatta V. Bodas , Sundaravarathan R. Iyengar , Feranak Nelson , John M. Powell, Jr. , Suresh Sugumar
CPC分类号： G06F1/3287 , G06F1/26 , G06F1/329 , G06F9/5094 , Y02D10/22 , Y02D10/24
摘要： In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.
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3.发明授权Controlling power consumption in processor-based systems and components thereof 有权控制基于处理器的系统及其组件的功耗公开(公告)号：US09568978B2
公开(公告)日：2017-02-14
申请号：US14037686
申请日：2013-09-26
申请人： Intel Corporation
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3243 , G06F1/3293 , Y02D10/122 , Y02D10/152
摘要： Since the maximum power consumption is largely a concern at the power supply domain, a limited number of nodes may be allowed to consume their maximum power consumption by preventing other nodes from consuming their maximum power consumption. This approach may be used either instead of or in cooperation with existing maximum power consumption regulators.
摘要翻译： 由于电力供应领域的最大功耗主要受到关注，因此通过防止其他节点消耗其最大功耗，可以允许有限数量的节点消耗最大功耗。 这种方法可以用于现有的最大功耗调节器，也可以与现有的最大功耗调节器配合使用。
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公开(公告)号：US09557804B2
公开(公告)日：2017-01-31
申请号：US14867490
申请日：2015-09-28
申请人： Intel Corporation
发明人： Ankush Varma , Krishnakanth V. Sistla , Cesar A. Quiroz , Vivek Garg , Martin T. Rowland , Inder M. Sodhi , James S. Burns
CPC分类号： G06F1/3287 , G06F1/26 , G06F1/324 , G06F1/3275 , G06F1/3296 , Y02D10/126 , Y02D10/14 , Y02D10/172
摘要： A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.
摘要翻译： 一种用于在平台中的模块之间动态功率限制共享的方法和装置。 在本发明的一个实施例中，平台包括处理器和存储器模块。 通过扩展功率域以包括处理器和存储器模块，可以实现处理器和存储器模块之间的平台功率预算的动态共享。 对于低带宽工作负载，功率预算的动态共享为处理器通过使用存储器电源中的余量增加频率提供了重要机会，反之亦然。 这在本发明的一个实施例中能够实现相同的总平台功率预算的更高峰值性能。
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公开(公告)号：US09502082B1
公开(公告)日：2016-11-22
申请号：US14748728
申请日：2015-06-24
申请人： Intel Corporation
CPC分类号： G11C5/147 , G06F1/26 , G06F1/3225 , G06F1/3275 , G06F1/3296 , G11C5/14 , G11C11/005 , G11C11/2297 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Methods, apparatuses, and systems may provide a sensor to monitor a power consumption of a non-volatile random access memory (RAM) and a volatile RAM. A switch, connected to an output of the sensor, controls power to the non-volatile RAM, and a voltage regulator regulates a voltage of the non-volatile RAM and the volatile RAM. One or more memory slots receive the non-volatile RAM and the volatile RAM, and a processor receives information from the sensor, and controls the voltage regulator based on the received information. The voltage regulator comprises a plurality of registers to store power consumption information of the non-volatile RAM and the volatile RAM.
摘要翻译： 方法，设备和系统可以提供传感器以监视非易失性随机存取存储器（RAM）和易失性RAM的功耗。 连接到传感器输出的开关控制非易失性RAM的电源，电压调节器调节非易失性RAM和易失性RAM的电压。 一个或多个存储器插槽接收非易失性RAM和易失性RAM，并且处理器从传感器接收信息，并且基于接收到的信息来控制电压调节器。 电压调节器包括多个寄存器以存储非易失性RAM和易失性RAM的功耗信息。
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6.发明授权Method and system for run-time reallocation of leakage current and dynamic power supply current 有权运行时重新分配漏电流和动态电源电流的方法和系统公开(公告)号：US09335813B2
公开(公告)日：2016-05-10
申请号：US13903744
申请日：2013-05-28
申请人： Intel Corporation
CPC分类号： G06F1/324 , G06F1/206 , G06F1/26 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/329
摘要： A method and system for dynamic or run-time reallocation of leakage current and dynamic power supply current of a processor. In one embodiment of the invention, the processor uses the variation in the leakage current of the processor to reduce the maximum current dissipation or power supply current of the processor (ICCmax). By reducing the maximum current dissipation, the system cost can be reduced as a less expensive power delivery system is required in one embodiment of the invention.
摘要翻译： 一种用于处理器的漏电流和动态电源电流的动态或运行时重新分配的方法和系统。 在本发明的一个实施例中，处理器使用处理器的漏电流的变化来减小处理器的最大电流消耗或电源电流（ICCmax）。 通过减少最大电流消耗，可以减少系统成本，因为在本发明的一个实施例中需要较便宜的电力输送系统。
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