公开(公告)号：US20180004445A1

公开(公告)日：2018-01-04

申请号：US15201443

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： TOMER STARK ,  RON GABOR ,  JOSEPH NUZMAN

IPC: G06F3/06 ,  G06F12/14 ,  G06F12/06 ,  G06F11/07

CPC classification number: G06F12/0623 ,  G06F11/0727 ,  G06F11/073 ,  G06F12/14 ,  G06F2212/1052 ,  G06F2212/657

Abstract: One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.

公开(公告)号：US20190235938A1

公开(公告)日：2019-08-01

申请号：US16259736

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： TOMER STARK ,  RON GABOR ,  JOSEPH NUZMAN

IPC: G06F11/07 ,  G06F12/06 ,  G06F12/14

CPC classification number: G06F11/073 ,  G06F11/0727 ,  G06F12/0623 ,  G06F12/14 ,  G06F2212/1052 ,  G06F2212/657

Abstract: One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.

公开(公告)号：US20210200686A1

公开(公告)日：2021-07-01

申请号：US16728573

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： RON GABOR ,  RAANAN SADE ,  IGOR YANOVER ,  ASSAF ZALTSMAN ,  TOMER STARK

IPC: G06F12/1009 ,  G06F9/30

Abstract: An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.

公开(公告)号：US20210200684A1

公开(公告)日：2021-07-01

申请号：US16728527

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： RON GABOR ,  ENRICO PERLA ,  RAANAN SADE ,  IGOR YANOVER ,  TOMER STARK ,  JOSEPH NUZMAN

IPC: G06F12/0895 ,  G06F12/1081 ,  G06F12/1009 ,  G06F12/0811 ,  G06F12/14 ,  G06F9/30 ,  G06F11/30

Abstract: An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.