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公开(公告)号：US20210200860A1
公开(公告)日：2021-07-01
申请号：US16728843
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： ALEXANDER GENDLER , SAGI MELLER , GAVRI BERGER , IGOR YANOVER
Abstract: An apparatus and method for intelligent power virus protection in a processor. For example, one embodiment of a processor comprises: first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction; detection circuitry to detect one or more instructions of a particular type and/or width; evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry when executing the one or more instructions based on the detected instruction types and/or widths; and control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.
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公开(公告)号：US20170351641A1
公开(公告)日：2017-12-07
申请号：US15490743
申请日：2017-04-18
Applicant: Intel Corporation
Inventor： ZEEV SPERBER , ROBERT VALENTINE , SHLOMO RAIKIN , STANISLAV SHWARTSMAN , GAL OFIR , IGOR YANOVER , GUY PATKIN , OFER LEVY
CPC classification number: G06F15/7839 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/3808 , G06F9/383
Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.
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公开(公告)号：US20210200686A1
公开(公告)日：2021-07-01
申请号：US16728573
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： RON GABOR , RAANAN SADE , IGOR YANOVER , ASSAF ZALTSMAN , TOMER STARK
IPC: G06F12/1009 , G06F9/30
Abstract: An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.
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公开(公告)号：US20210200684A1
公开(公告)日：2021-07-01
申请号：US16728527
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： RON GABOR , ENRICO PERLA , RAANAN SADE , IGOR YANOVER , TOMER STARK , JOSEPH NUZMAN
IPC: G06F12/0895 , G06F12/1081 , G06F12/1009 , G06F12/0811 , G06F12/14 , G06F9/30 , G06F11/30
Abstract: An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.
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