公开(公告)号：US20170245390A1

公开(公告)日：2017-08-24

申请号：US15047454

申请日：2016-02-18

Applicant: Intel Corporation

Inventor： Thane M. Larson

IPC: H05K7/14 ,  H05K7/18 ,  F16M11/00

CPC classification number: H05K7/1492 ,  H04Q1/13 ,  H05K5/0021 ,  H05K7/1425 ,  H05K7/1488 ,  H05K7/1498 ,  H05K7/18 ,  H05K7/183

Abstract: Apparatuses and systems associated with a server rack to hold a plurality of rack components may include a cabinet having a front opening of width W, and a first mounting pole and a second mounting pole located parallel to each other at the front opening to facilitate receipt and to hold the plurality of rack components. The server rack may further include the first and second mounting poles having a spacing of x inches or centimeters from each other, with the mid-point of the spacing being offset from the mid-point of width W, that defines a first mounting space to receive a first subset of the rack components in a first orientation and a second mounting space to receive a second subset of the rack components in a second orientation that differs from the first orientation. Other embodiments may be described and/or claimed.

公开(公告)号：US10804631B2

公开(公告)日：2020-10-13

申请号：US16436743

申请日：2019-06-10

Applicant: Intel Corporation

Inventor： Timothy Wig ,  Manisha M. Nilange ,  Thane M. Larson ,  Horthense Delphine Tamdem

IPC: H05K1/00 ,  H01R12/73 ,  H01R12/70

Abstract: A device includes a circuit board with circuit components, and first edge finger tab extending from the circuit board, and a second edge finger tab extending from the circuit board. The first edge finger tab includes electrical contacts to provide signaling to and from particular circuit components of the circuit board, and is to mate with a Peripheral Component Interconnect Express (PCIe)-compatible edge card connection mechanism of a baseboard. The second edge finger tab includes electrical contacts to provide power delivery to the circuit board, is to mate with a second edge card connection mechanism of the baseboard. In some aspects, the second edge finger tab may be a PCIe-compatible feature that is typically to prevent the device from being inserted into a legacy PCI edge card connection mechanism, or with a PCIe-compatible feature that is typically to engage a retention mechanism of a baseboard.

公开(公告)号：US20190053397A1

公开(公告)日：2019-02-14

申请号：US15870721

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Thane M. Larson ,  Vasudevan Srinivasan ,  Murugasmy K. Nachimuthu ,  Brian J. Griffith

IPC: H05K7/14

Abstract: The present disclosure describes a number of embodiments related to devices, systems, and methods for identifying a location of a resource among a plurality of locations in a data center rack. A signal transmission medium may be disposed proximate to the plurality of locations to transmit a signal traversing the plurality of locations, with each resource in the rack having a sensor or transmitter portion that couples itself to the signal transmission medium at a point substantially at this resource location, or the location of the resource within the data center rack is identified based at least in part on the sensed signal.

公开(公告)号：US20190296470A1

公开(公告)日：2019-09-26

申请号：US16436743

申请日：2019-06-10

Applicant: Intel Corporation

Inventor： Timothy Wig ,  Manisha M. Nilange ,  Thane M. Larson ,  Horthense Delphine Tamdem

IPC: H01R12/73 ,  H01R12/70

Abstract: A device includes a circuit board with circuit components, and first edge finger tab extending from the circuit board, and a second edge finger tab extending from the circuit board. The first edge finger tab includes electrical contacts to provide signaling to and from particular circuit components of the circuit board, and is to mate with a Peripheral Component Interconnect Express (PCIe)-compatible edge card connection mechanism of a baseboard. The second edge finger tab includes electrical contacts to provide power delivery to the circuit board, is to mate with a second edge card connection mechanism of the baseboard. In some aspects, the second edge finger tab may be a PCIe-compatible feature that is typically to prevent the device from being inserted into a legacy PCI edge card connection mechanism, or with a PCIe-compatible feature that is typically to engage a retention mechanism of a baseboard.

公开(公告)号：US10222823B2

公开(公告)日：2019-03-05

申请号：US14750159

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Thane M. Larson ,  Ramamurthy Krithivas ,  Chris Ruffin

IPC: G06F1/14 ,  G06F9/4401 ,  G06F1/3203

Abstract: The present disclosure describes embodiments of apparatuses and methods related to a computing apparatus with a real time clock (RTC) coupled to a bus, where the RTC does not have a backup power source to maintain time and date of the RTC. The computing apparatus may have firmware coupled to the bus, and the firmware may contain boot logic with network time protocol (NTP) logic. The computing apparatus may have persistent memory coupled to the bus with configuration parameters. The computing apparatus may have a controller coupled to the bus, where the controller is to retrieve the configuration parameters from the persistent memory and processes the boot logic with the NTP logic using the configuration parameters to transmit an NTP request over the bus and receives a coordinated universal time (UTC) over the bus and stores the UTC in the RTC.

公开(公告)号：US10091906B2

公开(公告)日：2018-10-02

申请号：US15047454

申请日：2016-02-18

Applicant: Intel Corporation

Inventor： Thane M. Larson

IPC: H05K7/14 ,  H05K7/18 ,  H05K5/00 ,  H04Q1/02

Abstract: Apparatuses and systems associated with a server rack to hold a plurality of rack components may include a cabinet having a front opening of width W, and a first mounting pole and a second mounting pole located parallel to each other at the front opening to facilitate receipt and to hold the plurality of rack components. The server rack may further include the first and second mounting poles having a spacing of x inches or centimeters from each other, with the mid-point of the spacing being offset from the mid-point of width W, that defines a first mounting space to receive a first subset of the rack components in a first orientation and a second mounting space to receive a second subset of the rack components in a second orientation that differs from the first orientation. Other embodiments may be described and/or claimed.

公开(公告)号：US20160378135A1

公开(公告)日：2016-12-29

申请号：US14750159

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Thane M. Larson ,  Ramamurthy Krithivas ,  Chris Ruffin

IPC: G06F1/14 ,  G06F9/44

CPC classification number: G06F1/14 ,  G06F1/3203 ,  G06F9/4401

Abstract: The present disclosure describes embodiments of apparatuses and methods related to a computing apparatus with a real time clock (RTC) coupled to a bus, where the RTC does not have a backup power source to maintain time and date of the RTC. The computing apparatus may have firmware coupled to the bus, and the firmware may contain boot logic with network time protocol (NTP) logic. The computing apparatus may have persistent memory coupled to the bus with configuration parameters. The computing apparatus may have a controller coupled to the bus, where the controller is to retrieve the configuration parameters from the persistent memory and processes the boot logic with the NTP logic using the configuration parameters to transmit an NTP request over the bus and receives a coordinated universal time (UTC) over the bus and stores the UTC in the RTC.

Abstract translation: 本公开描述了与具有耦合到总线的实时时钟（RTC）的计算装置相关的装置和方法的实施例，其中RTC没有备用电源来维持RTC的时间和日期。 计算设备可以具有耦合到总线的固件，并且固件可以包含具有网络时间协议（NTP）逻辑的引导逻辑。 计算设备可以具有通过配置参数耦合到总线的持久存储器。 计算设备可以具有耦合到总线的控制器，其中控制器将从持久存储器检索配置参数，并使用配置参数使用NTP逻辑处理引导逻辑，以通过总线发送NTP请求，并且接收协调 通用时间（UTC），并将UTC存储在RTC中。