公开(公告)号：US20240202415A1

公开(公告)日：2024-06-20

申请号：US18068601

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Quan Shi ,  Patrick Morrow ,  Charles Henry Wallace ,  Lars Liebmann ,  Thi Nguyen ,  Sivakumar Venkataraman ,  Nikolay Ryzhenko Vladimirovich ,  Xinning Wang ,  Douglas Stout

IPC: G06F30/392 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/394 ,  G06F2119/18

Abstract: Transistor cell architectures have three MO routing tracks within a single cell height. The cell architectures include at least one p-type transistor formed over a p-type diffusion region and at least one n-type transistor formed over an n-type diffusion region. Each diffusion region extends primarily in a particular direction, and the MO routing tracks extending in the same direction as the diffusion regions. One MO routing track may be formed over each of the diffusion regions, and a third MO routing track formed between the diffusion regions.