公开(公告)号：US20230162902A1

公开(公告)日：2023-05-25

申请号：US17531954

申请日：2021-11-22

申请人： Intel Corporation

发明人： Numair Ahmed ,  Kyu Oh Lee ,  Sri Chaitra Jyotsna Chavali ,  Vijaya Boddu ,  Krishna Bharath ,  Robert L. Sankman

IPC分类号： H01F27/02 ,  H01F41/02 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01F27/022 ,  H01F41/0206 ,  H01L23/49822 ,  H01L23/49827 ,  H01L21/4857 ,  H01L21/486

摘要： An electronic device and associated methods are disclosed. In one example, the electronic device includes a package with integrated inductors. In selected examples, the package includes a core layer having a core thickness and through holes. The package further includes inductor structures within the through holes, such that an inductor structure has a length exceeding the core thickness.

公开(公告)号：US20210183846A1

公开(公告)日：2021-06-17

申请号：US17185504

申请日：2021-02-25

申请人： Intel Corporation

发明人： Jeffory L. Smalley ,  Thomas Holden ,  Russell J. Wunderlich ,  Farzaneh Yahyaei-Moayyed ,  Mohanraj Prabhugoud ,  Horthense Delphine Tamdem ,  Vijaya Boddu ,  Kaladhar Radhakrishnan ,  Timothy Glen Hanna ,  Krishna Bharath ,  Judy Amanor-Boadu ,  Mark A. Schmisseur ,  Srikant Nekkanty ,  Luis E. Rosales Galvan

IPC分类号： H01L25/18 ,  H01L23/498 ,  H01R12/71

摘要： A processor module comprises an integrated circuit component attached to a power interposer. One or more voltage regulator modules attach to the power interposer via interconnect sockets and the power interposer routes regulated power signals generated by the voltage regulator modules to the integrated circuit component. Input power signals are provided to the voltage regulator from the system board via straight pins, a cable connector, or another type of connector. The integrated circuit component's I/O signals are routed through the power interposer to a system board via a socket located between the power interposer and the socket. Not having to route regulated power signals from a system board through a socket to an integrated circuit component can result in a system board with fewer layers, which can reduce overall system cost, as well as creating more area available in the remaining layers for I/O signal entry to the socket.