公开(公告)号：US20240327201A1

公开(公告)日：2024-10-03

申请号：US18192576

申请日：2023-03-29

Applicant: Intel Corporation

Inventor： Numair Ahmed ,  Mohammad Mamunur Rahman ,  Suddhasattwa Nad ,  Sashi Kandanur ,  Darko Grujicic ,  Benjamin Duong ,  Srinivas Pietambaram ,  Tarek Ibrahim ,  Whitney Bryks

IPC: B81B7/00 ,  B81C1/00 ,  G02B6/12

CPC classification number: B81B7/0048 ,  B81C1/00325 ,  G02B6/12004 ,  B81B2201/0228 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/0278 ,  B81B2201/03 ,  B81B2201/045 ,  B81B2207/07 ,  B81B2207/096 ,  B81B2207/097

Abstract: MEMS dies embedded in glass cores of integrated circuit (IC) package substrates are disclosed. An example integrated circuit (IC) package includes a package substrate including a glass core, the example integrated circuit (IC) package also includes a micro electromechanical system (MEMS) die positioned in a cavity of the glass core.

公开(公告)号：US20230317642A1

公开(公告)日：2023-10-05

申请号：US17707523

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Numair Ahmed ,  Cary Kuliasha ,  Kyu Oh Lee ,  Jung Kyu Han

IPC: H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L21/48

CPC classification number: H01L23/645 ,  H01L23/49827 ,  H01L21/486 ,  H01L28/10 ,  H01L23/49838

Abstract: A substrate for an electronic device may include a core. The substrate may include a passive electronic component. For instance, the substrate may include a continuous layer of molding material encapsulating the passive electronic component within the core. One or more through vias may extend between a first surface of the core and a second surface of the core. The substrate may include one or more layers coupled with the core. One or more component terminals may facilitate electrical communication between the passive electronic component and one or more of the first layer or the second layer.

公开(公告)号：US20240222018A1

公开(公告)日：2024-07-04

申请号：US18147503

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Thomas Sounart ,  Henning Braunisch ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Numair Ahmed ,  Darko Grujicic ,  Suddhasattwa Nad ,  Benjamin Duong ,  Marcel Wall ,  Shayan Kaviani

IPC: H01G4/01 ,  H01G4/30 ,  H01G4/33 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01G4/01 ,  H01G4/306 ,  H01G4/33 ,  H01L21/4846 ,  H01L23/5386 ,  H01L28/87 ,  H01L28/92 ,  H01G4/008

Abstract: Substrate package-integrated oxide capacitors and related methods are disclosed herein. An example apparatus including a first layer and a thin film capacitor including a second layer on the first layer, the second layer defining a plurality of openings and a third layer disposed on the first layer and in the plurality of openings, the second layer and the third layer corresponding to electrodes of a capacitor and a fourth layer disposed between the first layer and the second layer, the third layer including an oxidized material, the third layer forming a dielectric of the capacitor.

公开(公告)号：US20230092492A1

公开(公告)日：2023-03-23

申请号：US17480064

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Xin Ning ,  Brandon C. Marin ,  Kyu Oh Lee ,  Siddharth K. Alur ,  Numair Ahmed ,  Brent Williams ,  Mollie Stewart ,  Nathan Ou ,  Cary Kuliasha

IPC: H01L23/64 ,  H01F27/28 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48

Abstract: Transmission pathways in substrates, and associated methods are shown. Example transmission pathways include a semiconductor substrate with a core, a dielectric layer fixed on the core, at least one first electrical transmission pathway extending through at least one of the dielectric layer and the core. The first pathway includes a magnetic material disposed within the at least the core of the at least one first electrical transmission pathway, at least one second electrical transmission pathway extending through the magnetic material, a nickel layer disposed on inner circumferential surface of the magnetic material at least within the second electrical transmission pathway, a copper layer disposed on at least the nickel layer within the second electrical transmission pathway. The dielectric spacer or the nickel layer separates the copper layer from the magnetic material. At least one third pathway extends through at least one of the dielectric layer and the core separate from the at least one electrical transmission pathway.

公开(公告)号：US12224253B2

公开(公告)日：2025-02-11

申请号：US17480064

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Xin Ning ,  Brandon C. Marin ,  Kyu Oh Lee ,  Siddharth K. Alur ,  Numair Ahmed ,  Brent Williams ,  Mollie Stewart ,  Nathan Ou ,  Cary Kuliasha

IPC: H01L23/64 ,  H01F27/28 ,  H01L21/48 ,  H01L23/498 ,  H01L49/02

Abstract: Transmission pathways in substrates, and associated methods are shown. Example transmission pathways include a semiconductor substrate with a core, a dielectric layer fixed on the core, at least one first electrical transmission pathway extending through at least one of the dielectric layer and the core. The first pathway includes a magnetic material disposed within the at least the core of the at least one first electrical transmission pathway, at least one second electrical transmission pathway extending through the magnetic material, a nickel layer disposed on inner circumferential surface of the magnetic material at least within the second electrical transmission pathway, a copper layer disposed on at least the nickel layer within the second electrical transmission pathway. The dielectric spacer or the nickel layer separates the copper layer from the magnetic material. At least one third pathway extends through at least one of the dielectric layer and the core separate from the at least one electrical transmission pathway.

公开(公告)号：US20240395661A1

公开(公告)日：2024-11-28

申请号：US18202046

申请日：2023-05-25

Applicant: Intel Corporation

Inventor： Numair Ahmed ,  Suddhasattwa Nad ,  Mohammad Mamunur Rahman ,  Brandon C. Marin ,  Sashi S. Kandanur ,  Srinivas Venkata Ramanuja Pietambaram ,  Darko Grujicic ,  Gang Duan ,  Banjamin Duong

IPC: H01L23/473 ,  H01L23/31 ,  H01L23/373 ,  H01L23/48 ,  H01L23/498

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a glass core layer having a first surface layer and a second surface layer; multiple channels within the glass core layer between the first surface and the second surface layer; and a first redistribution layer (RDL) including multiple sublayers of conductive traces formed in an organic material, wherein a first surface of the RDL contacts the first surface of the glass core layer.

公开(公告)号：US11735551B2

公开(公告)日：2023-08-22

申请号：US16363996

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Shawna Liff ,  Xin Yan ,  Numair Ahmed

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13014 ,  H01L2224/1319 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/171 ,  H01L2224/812 ,  H01L2224/81139 ,  H01L2224/81815 ,  H01L2924/014

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to an interconnect joint that includes multiple core balls within a solder compound where the multiple core balls are substantially linearly aligned. The multiple core balls, which may include copper or be a polymer, couple with each other within the solder and form a substantially linear alignment during reflow. In embodiments, four or more core balls may be used to achieve a high aspect ratio interconnect joint with a tight pitch.

公开(公告)号：US20230162902A1

公开(公告)日：2023-05-25

申请号：US17531954

申请日：2021-11-22

Applicant: Intel Corporation

Inventor： Numair Ahmed ,  Kyu Oh Lee ,  Sri Chaitra Jyotsna Chavali ,  Vijaya Boddu ,  Krishna Bharath ,  Robert L. Sankman

IPC: H01F27/02 ,  H01F41/02 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01F27/022 ,  H01F41/0206 ,  H01L23/49822 ,  H01L23/49827 ,  H01L21/4857 ,  H01L21/486

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a package with integrated inductors. In selected examples, the package includes a core layer having a core thickness and through holes. The package further includes inductor structures within the through holes, such that an inductor structure has a length exceeding the core thickness.