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    High density package substrate formed with dielectric bi-layer
    2.
    发明授权
    High density package substrate formed with dielectric bi-layer 有权

    公开(公告)号：US11276634B2

    公开(公告)日：2022-03-15

    申请号：US16607601

    申请日：2017-05-23

    Applicant: Intel Corporation

    Inventor： Srinivas V. Pietambaram ,  Rahul N. Manepalli ,  David Unruh ,  Frank Truong ,  Kyu Oh Lee ,  Junnan Zhao ,  Sri Chaitra Jyotsna Chavali

    IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48

    Abstract: Disclosed herein are integrated circuit (IC) package substrates formed with a dielectric bi-layer, and related devices and methods. In some embodiments, an IC package substrate is fabricated by: forming a raised feature on a conductive layer; forming a dielectric bi-layer on the conductive layer, where the dielectric bi-layer includes a first sub-layer having a first material property and a second sub-layer having a second material property, and where the top surface of the second sub-layer is substantially planar with the top surface of the raised feature; and removing the first sub-layer until the second material property is detected to reveal the conductive feature. In some embodiments, an IC package substrate is fabricated by: forming a dielectric bi-layer on a patterned conductive layer, where the first sub-layer is less susceptible to removal than the second sub-layer; forming an opening in the dielectric bi-layer; etching; and forming a via having vertical sidewalls.

    Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate
    3.
    发明授权
    Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate 有权

    公开(公告)号：US11139264B2

    公开(公告)日：2021-10-05

    申请号：US16586820

    申请日：2019-09-27

    Applicant: Intel Corporation

    Inventor： Rahul Jain ,  Ji Yong Park ,  Kyu Oh Lee

    IPC: H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065

    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

    HIGH DENSITY PACKAGE SUBSTRATE FORMED WITH DIELECTRIC BI-LAYER
    5.
    发明申请
    HIGH DENSITY PACKAGE SUBSTRATE FORMED WITH DIELECTRIC BI-LAYER 审中-公开

    公开(公告)号：US20200075473A1

    公开(公告)日：2020-03-05

    申请号：US16607601

    申请日：2017-05-23

    Applicant: Intel Corporation

    Inventor： Srinivas V. Pietambaram ,  Rahul N. Manepalli ,  David Unruh ,  Frank Truong ,  Kyu Oh Lee ,  Junnan Zhao ,  Sri Chaitra Jyotsna Chavali

    IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48

    Abstract: Disclosed herein are integrated circuit (IC) package substrates formed with a dielectric bi-layer, and related devices and methods. In some embodiments, an IC package substrate is fabricated by: forming a raised feature on a conductive layer; forming a dielectric bi-layer on the conductive layer, where the dielectric bi-layer includes a first sub-layer having a first material property and a second sub-layer having a second material property, and where the top surface of the second sub-layer is substantially planar with the top surface of the raised feature; and removing the first sub-layer until the second material property is detected to reveal the conductive feature. In some embodiments, an IC package substrate is fabricated by: forming a dielectric bi-layer on a patterned conductive layer, where the first sub-layer is less susceptible to removal than the second sub-layer; forming an opening in the dielectric bi-layer; etching; and forming a via having vertical sidewalls.

    Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate
    6.
    发明授权
    Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate 有权

    公开(公告)号：US10468374B2

    公开(公告)日：2019-11-05

    申请号：US15475175

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Rahul Jain ,  Ji Yong Park ,  Kyu Oh Lee

    IPC: H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

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