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公开(公告)号：US20240022254A1
公开(公告)日：2024-01-18
申请号：US17864593
申请日：2022-07-14
Applicant: Intel Corporation
Inventor： Hongjiang Song , Mingming Xu , Vijayalakshmi Ramachandran
Abstract: An apparatus, system, and method for low frequency periodic signaling (LFPS) and/or squelch detection are provided. A circuit can include a threshold generator situated to receive a differential input signal from an initiator device and generate a differential voltage threshold signal based on the differential input signal, an amplifier circuit electrically coupled to the threshold generator situated to amplify the differential voltage threshold signal resulting in an amplified threshold signal, a sampler situated to sample the amplified threshold signal at a first clock rate faster than a clock rate of an LFPS/squelch signaling frequency resulting in digital sample results, and a pattern filter circuit situated to determine if the digital sample results are asserted for each of a specified number of consecutive clock cycles at the first clock rate.
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2.发明公开公开(公告)号：US20230367725A1
公开(公告)日：2023-11-16
申请号：US17743297
申请日：2022-05-12
Applicant: Intel Corporation
Inventor： Vijayalakshmi Ramachandran , Mingming Xu , Dror Lazar
CPC classification number: G06F13/20 , G01R31/2889 , G05F1/46 , G06F2213/40
Abstract: Techniques and mechanisms for determining a reference voltage which is to be provided with an integrated circuit (IC) die. In an embodiment, the IC die comprises a resistor, and a hardware interface which accommodates coupling of the IC die to a test unit. The test unit provides functionality to perform an evaluation of a resistance of the resistor, wherein said resistance is indicative of the respective resistances of one or more other resistors of the IC die. Based on the evaluation, the test unit provides to the IC die an indication of a scale factor, wherein the reference voltage is generated based on the scale factor. In another embodiment, the IC die further comprises an amplifier circuit which receives the reference voltage, wherein a variable resistance circuit of the IC die is configured based on an output of the amplifier circuit.
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3.发明授权公开(公告)号：US12066959B2
公开(公告)日：2024-08-20
申请号：US17743297
申请日：2022-05-12
Applicant: Intel Corporation
Inventor： Vijayalakshmi Ramachandran , Mingming Xu , Dror Lazar
CPC classification number: G06F13/20 , G01R31/2889 , G05F1/46 , G06F2213/40
Abstract: Techniques and mechanisms for determining a reference voltage which is to be provided with an integrated circuit (IC) die. In an embodiment, the IC die comprises a resistor, and a hardware interface which accommodates coupling of the IC die to a test unit. The test unit provides functionality to perform an evaluation of a resistance of the resistor, wherein said resistance is indicative of the respective resistances of one or more other resistors of the IC die. Based on the evaluation, the test unit provides to the IC die an indication of a scale factor, wherein the reference voltage is generated based on the scale factor. In another embodiment, the IC die further comprises an amplifier circuit which receives the reference voltage, wherein a variable resistance circuit of the IC die is configured based on an output of the amplifier circuit.
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