公开(公告)号：US20210247937A1

公开(公告)日：2021-08-12

申请号：US17241976

申请日：2021-04-27

Applicant: Intel Corporation

Inventor： Vivek Angoth ,  David Carlton ,  Sarvesh Gangadhar ,  MarkAnthony Golez ,  David J. Pelster ,  Neelesh Vemula

IPC: G06F3/06

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to NAND-based storage media that includes a plurality of NAND devices, determine if a current workload for a particular NAND device of the plurality of NAND devices is a random write workload, and, if so determined, disable a program suspend operation for only the particular NAND device. Other embodiments are disclosed and claimed.

公开(公告)号：US20230044991A1

公开(公告)日：2023-02-09

申请号：US17393877

申请日：2021-08-04

Applicant: Intel Corporation

Inventor： Shantanu Rajwade ,  Kartik Ganapathi ,  Rohit Shenoy ,  Kristopher Gaewsky ,  MarkAnthony Golez ,  Vivek Angoth ,  Pranav Kalavade ,  Sarvesh Gangadhar

IPC: G06F3/06

Abstract: Systems, apparatuses and methods may provide for technology that detects a request to program a NAND memory containing a plurality of dies and programs the NAND memory on a stripe-by-stripe basis, wherein each stripe spans the plurality of dies and includes multiple types of pages. The multiple types of pages may reduce program time variability across the stripes and reduce the error susceptibility of the NAND memory.

公开(公告)号：US10452574B2

公开(公告)日：2019-10-22

申请号：US16046850

申请日：2018-07-26

Applicant: Intel Corporation

Inventor： Vivek Angoth ,  Hung Huynh ,  Daniel McLeran

IPC: G06F13/376 ,  G06F13/16 ,  G06F13/42 ,  G06F13/38

Abstract: Examples may include a storage device coupled to a host bus adapter and a SATA controller over a SATA interface. The storage device includes a memory and a storage device controller. The storage device controller includes a collision detector and counter component to detect and count collisions on the SATA interface for a period of time; and a bus limiter component to detect a type of workload on the SATA interface, and when the detected workload is only read commands and a number of detected collisions is less than a detected collision threshold during the period of time, to set a limit on a maximum number of commands sent by the host bus adapter to the storage device controller over the SATA interface.