公开(公告)号：US20240006302A1

公开(公告)日：2024-01-04

申请号：US17856777

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Richard H. Livengood ,  Muhammad Usman Raza ,  Waqas Ali ,  Tahir Malik ,  Shida Tan ,  Martin Von Haartman ,  Mauro Kobrinsky ,  Amir Raveh ,  Clifford J. Engle

IPC: H01L23/50 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L23/50 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/0873 ,  H01L29/42392 ,  H01L29/78696

Abstract: Techniques and structures are disclosed related to coupling to gate-all-around transistors for test and/or debug of an integrated circuit. The gate-all-around transistors, which may also be referred to as 3D stacked transistors or ribbon-FET transistors are contacted directly from the back side or they are contacted using a dedicated probe point on the back side of the gate-all-around transistors. Such contact may be made to probe the devices and/or to provide edit wires to modify the integrated circuit.