公开(公告)号：US20240222126A1

公开(公告)日：2024-07-04

申请号：US18147644

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Uygar Avci ,  Brandon Holybee ,  Jennifer Lux ,  Kevin O'Brien ,  Shida Tan

IPC: H01L21/266 ,  H01L21/265

CPC classification number: H01L21/266 ,  H01L21/26506

Abstract: This disclosure describes systems, apparatus, methods, and devices related to fabrication using ion beams. The device may apply an ion beam targeted to at least one of one or more regions of a top layer, a metal layer placed on top of the top layer, or one or more ion stoppers placed on top of the top layer, wherein the ion beam is tuned using a predetermined energy range or a dosing level of ions to modify the material characteristics of the 2D material at the one or more regions of the top layer. The device may create a bond between the one or more 2D and metal layers to the one or more regions of the top layer where the material characteristics of the 2D material have been modified due to the impinging ion beam.

公开(公告)号：US20240222073A1

公开(公告)日：2024-07-04

申请号：US18147636

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Shida Tan ,  Uygar Avci ,  Brandon Holybee ,  Kirby Maxey ,  Kevin O'Brien ,  Mahmut Sami Kavrik

IPC: H01J37/317 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01J37/3174 ,  H01L21/0279 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32135 ,  H01L21/32139 ,  H01J2237/3174 ,  H01J2237/31755

Abstract: This disclosure describes systems, apparatus, methods, and devices related to ion beams fabrication. A device may overlay a wafer assembly of one or more layers with a top layer comprised of a material having 2D material characteristics. The device may be fabricated by applying an ion beam targeted to at least one of one or more regions of the top layer or a resist layer placed on top of the top layer, wherein the ion beam is tuned using a predetermined energy range or a dosing level of ions to modify material characteristics of the resist layer or to perform milling of the top layer or other layers of the one or more layers of the wafer assembly.

公开(公告)号：US20240006302A1

公开(公告)日：2024-01-04

申请号：US17856777

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Richard H. Livengood ,  Muhammad Usman Raza ,  Waqas Ali ,  Tahir Malik ,  Shida Tan ,  Martin Von Haartman ,  Mauro Kobrinsky ,  Amir Raveh ,  Clifford J. Engle

IPC: H01L23/50 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L23/50 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/0873 ,  H01L29/42392 ,  H01L29/78696

Abstract: Techniques and structures are disclosed related to coupling to gate-all-around transistors for test and/or debug of an integrated circuit. The gate-all-around transistors, which may also be referred to as 3D stacked transistors or ribbon-FET transistors are contacted directly from the back side or they are contacted using a dedicated probe point on the back side of the gate-all-around transistors. Such contact may be made to probe the devices and/or to provide edit wires to modify the integrated circuit.