公开(公告)号：US20240329122A1

公开(公告)日：2024-10-03

申请号：US18128617

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Amit PALIWAL ,  Xiao WEN ,  Dipto THAKURTA

IPC: G01R31/28

CPC classification number: G01R31/2884

Abstract: A device under test (DUT) structure for voltage contrast (VC) detection of contact opens comprises a fin formed along a first direction over a substrate, the fin having a diffusion region, the fin doped to form i) a p-type fin and a p-type diffusion region or ii) an n-type fin and an n-type diffusion region. A trench contact (TCN) segment is along a second direction generally orthogonal to the first direction over the fin and in contact with the diffusion region. A floating gate is generally parallel to the TCN segment over the fin, wherein the floating gate and the TCN segment are not in contact, and the floating gate does not have a via formed thereon.

公开(公告)号：US20240006254A1

公开(公告)日：2024-01-04

申请号：US17855636

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Xiao WEN ,  Dipto THAKURTA ,  Sairam SUBRAMANIAN

IPC: H01L21/66 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L22/34 ,  H01L23/528 ,  H01L21/768

Abstract: Embodiments described herein may be related to apparatuses, systems, processes, and/or techniques for identifying device defects on a wafer substrate using voltage contrast techniques and electronic beam scans by scanning an area on a portion of the wafer that includes ends of a plurality of traces that extend from the scan area respectively to blocks on the wafer that include devices to be tested. During the electronic beam scan, ends of the plurality of traces within the scan area that are coupled with devices that are electrically shorted will appear bright, and those that are electrically open will appear dark. Other embodiments may be described and/or claimed.

公开(公告)号：US20240112962A1

公开(公告)日：2024-04-04

申请号：US17958281

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Xiao WEN ,  Dipto THAKURTA ,  Sairam SUBRAMANIAN ,  David SANCHEZ ,  Amit PALIWAL

IPC: H01L21/66 ,  G01R31/52

CPC classification number: H01L22/32 ,  G01R31/52 ,  G01R31/54

Abstract: Embodiments disclosed herein include an apparatus for alignment detection. In an embodiment, the apparatus comprises a substrate, and a plurality of devices on the substrate, where each of the plurality of devices comprises a process monitor structure with different offsets from a target value. In an embodiment, a plurality of electrically conductive traces are on the substrate, where each of the plurality of electrically conductive traces has a first end and a second end opposite the first end, and where each of the plurality of electrically conductive traces is electrically coupled at the first end, respectively, with each of the plurality of devices. In an embodiment, the second end of the each of the plurality of electrical traces is within a scan area on the substrate, and where the each of the plurality of electrically conductive traces are not directly electrically coupled with each other.

公开(公告)号：US20240006501A1

公开(公告)日：2024-01-04

申请号：US17855632

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Xiao WEN ,  Dipto THAKURTA ,  Sairam SUBRAMANIAN ,  Manish SHARMA

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417 ,  H01L29/40

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/41791 ,  H01L29/401

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for electrically coupling components of a transistor structure together in order to perform a voltage contrast test to determine opens and shorts within the transistor structure. In embodiments, trench contacts (TCN) within a transistor structure may be electrically coupled together with an electrical connection that is electrically isolated from a power rail. In other embodiments, TCN may be electrically coupled using P-type epitaxial layers on a P-type substrate. Other embodiments may be described and/or claimed.