公开(公告)号：US09735813B2

公开(公告)日：2017-08-15

申请号：US15084329

申请日：2016-03-29

Applicant: Intel Corporation

Inventor： Shenggao Li ,  Xiaoqing Wang

IPC: H04L25/03 ,  H04B1/04 ,  H04B10/50 ,  H04L25/02

CPC classification number: H04B1/0475 ,  H04B10/503 ,  H04L25/0272 ,  H04L25/03878

Abstract: Described is an apparatus for boosting a transition edge of a signal, the apparatus comprises: a logic to provide input data having a Unit Interval (UI); a programmable delay unit to receive the input data and operable to delay the input data by a fraction of the UI to generate a delayed input data; and one or more drivers to drive the input data and the delayed input data to a node.

公开(公告)号：US09379743B2

公开(公告)日：2016-06-28

申请号：US14446664

申请日：2014-07-30

Applicant: Intel Corporation

Inventor： Shenggao Li ,  Xiaoqing Wang

IPC: H04B10/2507 ,  H04B1/04 ,  H04B10/50

CPC classification number: H04B1/0475 ,  H04B10/503 ,  H04L25/0272 ,  H04L25/03878

Abstract: Described is an apparatus for boosting a transition edge of a signal, the apparatus comprises: a logic to provide input data having a Unit Interval (UI); a programmable delay unit to receive the input data and operable to delay the input data by a fraction of the UI to generate a delayed input data; and one or more drivers to drive the input data and the delayed input data to a node.

Abstract translation: 描述了一种用于升高信号的过渡边缘的装置，该装置包括：提供具有单位间隔（UI）的输入数据的逻辑; 可编程延迟单元，用于接收所述输入数据并且可操作以通过所述UI的一小部分来延迟所述输入数据以产生延迟的输入数据; 以及用于将输入数据和延迟的输入数据驱动到节点的一个或多个驱动器。

公开(公告)号：US10063253B1

公开(公告)日：2018-08-28

申请号：US15629959

申请日：2017-06-22

Applicant: Intel Corporation

Inventor： Xiaoqing Wang ,  Shenggao Li

IPC: H03M3/00 ,  H04L25/03 ,  G06G7/14 ,  G06G7/186

CPC classification number: H03M3/452 ,  G06G7/14 ,  G06G7/1865 ,  H03M3/424 ,  H04L25/0292 ,  H04L25/03006 ,  H04L25/03012

Abstract: Some embodiments include apparatuses having a first circuit portion, a second circuit portion, and a third circuit portion. The first circuit portion includes a first transistor to receive a first signal of a differential signal pair and a second transistor to receive a second signal of the differential signal pair. The second circuit portion is coupled to the first and second transistors and a first supply node, the second circuit portion including a first output node and a second output node to provide an output signal pair based on the differential signal pair. The third circuit portion includes a first diode-connected transistor coupled between the first output node and a second supply node and a second diode-connected transistor coupled between the second output node and the second supply node.