公开(公告)号：US20230319997A1

公开(公告)日：2023-10-05

申请号：US17710944

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Aslam HASWAREY ,  Anne AUGUSTINE ,  Yan Fen SHEN

IPC: H05K1/16 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/0094 ,  H05K2201/09636 ,  H05K2201/0959 ,  H05K2201/09563 ,  H05K1/181

Abstract: Embodiments herein relate to systems, apparatuses, or processes to using vias, or plated through holes (PTH), within a substrate or within a sub laminate to create capacitors. The interior of a via may have a first layer, or coating, of an electrically conductive material such as copper, formed on the sides of the via. A second layer including a dielectric material is placed on the first layer of the electrically conductive material. A third layer of electrically conductive material may then be placed on the second layer of the dielectric material. Other embodiments may be described and/or claimed.