公开(公告)号：US20240306297A1

公开(公告)日：2024-09-12

申请号：US18601668

申请日：2024-03-11

申请人： Apple Inc.

发明人： Anne M. Mason ,  Chad O. Simpson ,  William Hannon ,  Mark J. Beesley

IPC分类号： H05K1/11 ,  H05K3/00 ,  H05K3/42

CPC分类号： H05K1/115 ,  H05K3/0047 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/107

摘要： Structures that implement three-dimensional (3D) conductive material (e.g., copper) in printed circuit boards (PCBs) are disclosed. 3D (three-dimensional) conductive material may include trenches and/or buried vias that are filled with conductive material in the PCBs. Trenches may be formed in build-up layers of a PCB by overlapping multiple laser drilled vias. The trenches may be filled with conductive material using electroplating process(es). Buried vias may be formed through the core layers of the PCB by mechanical drilling. The buried via may be filled with solid conductive material using a combination of electroless plating and electrolytic plating of conductive material. Various PCB structures are disclosed that implement combinations of these trenches and/or these buried vias filled with conductive material.

公开(公告)号：US20240282687A1

公开(公告)日：2024-08-22

申请号：US18650005

申请日：2024-04-29

申请人： Unimicron Technology Corp.

发明人： Chih-Chiang Lu ,  Hsin-Ning Liu ,  Jun-Rui Huang ,  Pei-Wei Wang ,  Ching Sheng Chen ,  Shih-Lian Cheng

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H05K1/02 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46

CPC分类号： H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H05K1/0222 ,  H05K3/0094 ,  H05K3/429 ,  H05K3/4614 ,  H05K3/4623 ,  H01L24/16 ,  H01L2224/16227 ,  H05K2201/09509 ,  H05K2201/0959

摘要： A manufacturing method of the circuit board includes the following steps. A metal layer, a first substrate, a second substrate, and a third substrate are laminated. Multiple blind holes and a through hole are formed. A conductive material layer is formed, which covers the metal layer, the conductive layer of the third substrate, and an inner wall of the through hole, and fills the blind holes to define multiple conductive holes. The conductive material layer, the metal layer, and the conductive layer are patterned to form a first external circuit layer located on the first substrate and electrically connected to the conductive pillars, and a second external circuit layer located on the insulating layer and electrically connected to the conductive holes, and define a conductive through hole structure connecting the first external circuit layer and the second external circuit layer and located in the through hole.

公开(公告)号：US12016128B2

公开(公告)日：2024-06-18

申请号：US17462157

申请日：2021-08-31

申请人： LG INNOTEK CO., LTD.

发明人： Min Young Hwang ,  Byeong Kyun Choi ,  Jin Seok Lee ,  Moo Seong Kim

IPC分类号： H05K3/10 ,  H05K1/09

CPC分类号： H05K3/10 ,  H05K1/09 ,  H05K2201/0355 ,  H05K2201/0358 ,  H05K2201/0959 ,  H05K2203/0723

摘要： A circuit board according to an embodiment includes an insulating layer; and a circuit pattern disposed on the insulating layer, wherein the circuit pattern includes a copper foil layer disposed on the insulating layer, a first plating layer disposed on the copper foil layer, and a second plating layer disposed on the first plating layer, and wherein the copper foil layer has a thickness in a range of 2 μm to 5 μm.

公开(公告)号：US11956898B2

公开(公告)日：2024-04-09

申请号：US17119126

申请日：2020-12-11

申请人： Apple Inc.

发明人： Anne M. Mason ,  Chad O. Simpson ,  William Hannon ,  Mark J. Beesley

IPC分类号： H05K1/11 ,  H05K3/00 ,  H05K3/42

CPC分类号： H05K1/115 ,  H05K3/0047 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/107

摘要： Structures that implement three-dimensional (3D) conductive material (e.g., copper) in printed circuit boards (PCBs) are disclosed. 3D (three-dimensional) conductive material may include trenches and/or buried vias that are filled with conductive material in the PCBs. Trenches may be formed in build-up layers of a PCB by overlapping multiple laser drilled vias. The trenches may be filled with conductive material using electroplating process(es). Buried vias may be formed through the core layers of the PCB by mechanical drilling. The buried via may be filled with solid conductive material using a combination of electroless plating and electrolytic plating of conductive material. Various PCB structures are disclosed that implement combinations of these trenches and/or these buried vias filled with conductive material.

公开(公告)号：US20240098897A1

公开(公告)日：2024-03-21

申请号：US18469675

申请日：2023-09-19

申请人： IBIDEN CO., LTD.

发明人： Yoshio MIZUTANI

IPC分类号： H05K1/11 ,  H05K3/00

CPC分类号： H05K1/113 ,  H05K3/0094 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09618

摘要： A wiring substrate includes an insulating layer having through holes, a first conductor layer formed on first surface of the insulating layer, a second conductor layer formed on second surface of the insulating layer, and interlayer conductors formed along wall surfaces surrounding the through holes such that each interlayer conductor has a film-like shape and is connecting the first and second conductor layers. The interlayer conductors include first conductors formed in first region of the insulating layer and second conductors formed in second region of the insulating layer at density higher than density of the first conductors, and a thickness of each first interlayer conductor in its end part is substantially same as or larger than a thickness of each second conductor in its end part and a thickness of each first conductor in its center part is larger than a thickness of each second conductor in its center part.

公开(公告)号：US20240008191A1

公开(公告)日：2024-01-04

申请号：US18342793

申请日：2023-06-28

申请人： IBIDEN CO., LTD.

发明人： Toshiki FURUTANI

IPC分类号： H05K3/46 ,  H05K1/11 ,  H05K3/18

CPC分类号： H05K3/4661 ,  H05K1/113 ,  H05K3/182 ,  H05K2201/096 ,  H05K2201/0959

摘要： A wiring substrate includes a first insulating layer, a conductor layer formed on the first insulating layer and including a wiring pattern, an organic coating film formed on the conductor layer such that the organic coating film is formed on the wiring pattern of the conductor layer, and a second insulating layer formed on the first insulating layer such that the second insulating layer is covering the conductor layer. The conductor layer is formed such that the wiring pattern has a polished surface on the opposite side with respect to the first insulating layer, and the organic coating film is formed on the wiring pattern of the conductor layer such that the organic coating film is covering the polished surface of the wiring pattern.

公开(公告)号：US11818833B2

公开(公告)日：2023-11-14

申请号：US17867624

申请日：2022-07-18

申请人： Unimicron Technology Corp.

发明人： Shih-Lian Cheng

IPC分类号： H05K1/02 ,  H01L23/498 ,  H05K1/14

CPC分类号： H05K1/0222 ,  H01L23/49822 ,  H01L23/49833 ,  H05K1/024 ,  H05K1/144 ,  H05K2201/098 ,  H05K2201/0959 ,  H05K2201/09672

摘要： A circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole electrically connected to the first and second external circuit layers, a first annular retaining wall surrounding the conductive through hole, and a second annular retaining wall surrounding the conductive through hole. The first annular retaining wall is electrically connected to the first external circuit layer and a first inner circuit layer. The second annular retaining wall is electrically connected to the second external circuit layer and a second inner circuit layer. A first ground circuit, the first annular retaining wall, and the first inner circuit layer define a first ground path surrounding a first signal circuit. A second ground circuit, the second annular retaining wall, and the second inner circuit layer define a second ground path surrounding a second signal circuit.

公开(公告)号：US20230354503A1

公开(公告)日：2023-11-02

申请号：US18344652

申请日：2023-06-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jiun-Yi WU ,  Chien-Hsun LEE ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

IPC分类号： H05K1/02 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

CPC分类号： H05K1/0216 ,  H05K1/024 ,  H01L21/76805 ,  H05K1/0222 ,  H01L21/485 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/552 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/4007 ,  H05K3/423 ,  H05K1/0245 ,  H05K3/42 ,  H05K2201/0959 ,  Y10T29/49165 ,  H05K3/4038 ,  H05K2201/0723 ,  H05K2201/09545 ,  H05K2201/09645

摘要： An interconnect structure includes a dielectric block, a first conductive plug, a second conductive plug, a substrate, a first conductive line, and a second conductive line. The first conductive plug and the second conductive plug are surrounded by the dielectric block. The substrate surrounds the dielectric block. The first conductive line is connected to the first conductive plug and is in contact with a top surface of the dielectric block. The second conductive line is connected to the second conductive plug.

公开(公告)号：US11778754B2

公开(公告)日：2023-10-03

申请号：US16777116

申请日：2020-01-30

申请人： AT&S Austria Technologie & Systemtechnik Aktiengesellschaft

发明人： Robin Zhang ,  Seok Kim Tay

IPC分类号： H05K3/42 ,  H05K1/18 ,  H05K1/11

CPC分类号： H05K3/429 ,  H05K1/115 ,  H05K1/186 ,  H05K3/423 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2203/1572

摘要： A component carrier includes an electrically insulating layer structure with a first main surface and a second main surface, a through hole extends through the electrically insulating layer structure between the first main surface and the second main surface. The through hole has a first tapering portion extending from the first main surface and a second tapering portion extending from the second main surface. The through hole is delimited by a first plating structure on at least part of the sidewalls of the electrically insulating layer structure and a second plating structure formed separately from and arranged on the first plating structure. The second plating structure includes an electrically conductive bridge structure connecting the opposing sidewalls.

公开(公告)号：US11737205B2

公开(公告)日：2023-08-22

申请号：US17884418

申请日：2022-08-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jiun-Yi Wu ,  Chien-Hsun Lee ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H01L23/552 ,  H05K3/42 ,  H05K1/02 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40

CPC分类号： H05K1/0216 ,  H01L21/485 ,  H01L21/486 ,  H01L21/76805 ,  H01L23/49827 ,  H01L23/552 ,  H05K1/024 ,  H05K1/0222 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/4007 ,  H05K3/423 ,  H05K1/0245 ,  H05K3/4038 ,  H05K3/42 ,  H05K2201/0723 ,  H05K2201/0959 ,  H05K2201/09545 ,  H05K2201/09645 ,  Y10T29/49165

摘要： An interconnect structure includes a first conductor, a second conductor, a dielectric block, a substrate, and a pair of conductive lines. The first conductor and the second conductor form a differential pair design. The dielectric block surrounds the first conductor and the second conductor. The first conductor is separated from the second conductor by the dielectric block. The substrate surrounds the dielectric block and is spaced apart from the first conductor and the second conductor. The pair of conductive lines is connected to the first conductor and the second conductor, respectively, and extends along a top surface of the dielectric block and a top surface of the substrate.