公开(公告)号：US20230319997A1

公开(公告)日：2023-10-05

申请号：US17710944

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Aslam HASWAREY ,  Anne AUGUSTINE ,  Yan Fen SHEN

IPC: H05K1/16 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/0094 ,  H05K2201/09636 ,  H05K2201/0959 ,  H05K2201/09563 ,  H05K1/181

Abstract: Embodiments herein relate to systems, apparatuses, or processes to using vias, or plated through holes (PTH), within a substrate or within a sub laminate to create capacitors. The interior of a via may have a first layer, or coating, of an electrically conductive material such as copper, formed on the sides of the via. A second layer including a dielectric material is placed on the first layer of the electrically conductive material. A third layer of electrically conductive material may then be placed on the second layer of the dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US20200258804A1

公开(公告)日：2020-08-13

申请号：US16858457

申请日：2020-04-24

Applicant: Intel Corporation

Inventor： Aslam HASWAREY ,  Kevin WELLS ,  Mehran ADYANI-YAZDI ,  Daniel R. RUSSELL ,  James C. MOWERY ,  Vinesh LAL ,  Xiangying MA

IPC: H01L23/34 ,  H01L27/02

Abstract: A thermal control circuit is described. The thermal control circuit includes a heating element disposed within an electronic circuit board having a semiconductor chip disposed thereon. The thermal control circuit includes a power management integrated circuit coupled to the heating element. The power management integrated circuit is to enable the heating element to heat the semiconductor chip at least to the semiconductor chips' lowest rated operating temperature prior to the semiconductor chip being placed in a fully operational state.