公开(公告)号：US20190103409A1

公开(公告)日：2019-04-04

申请号：US15721703

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Yi XU ,  Florence PON ,  Yong SHE

IPC: H01L27/112 ,  G06F17/50 ,  H01L21/768 ,  H01L23/525 ,  H03K19/177

CPC classification number: H01L27/1128 ,  G06F17/505 ,  G06F17/5068 ,  H01L21/768 ,  H01L23/5252 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/11206 ,  H01L2224/05554 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/8309 ,  H01L2224/83143 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/14 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1778 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012

Abstract: An IC package, comprising a substrate and two or more vertically stacked dies disposed within the substrate, wherein all the edges of the two or more dies are aligned with respect to one another, wherein at least two dies of the two or more vertically stacked dies are coupled directly to one another by at least one wire bonded to the ones of the at least two dies.

公开(公告)号：US20200343221A1

公开(公告)日：2020-10-29

申请号：US16392295

申请日：2019-04-23

Applicant: Intel Corporation

Inventor： Florence PON ,  Yi XU ,  James ZHANG ,  Yuhong CAI ,  Tyler LEUTEN ,  William GLENNAN ,  Hyoung Il KIM

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

Abstract: Embodiments described herein provide a semiconductor package comprising multiple dies encapsulated in multiple molding compounds. In one example, a semiconductor package comprises: a first die or die stack on a substrate; a first molding compound encapsulating the first die or die stack on the substrate; a second die or die stack on the first molding compound; and a second molding compound encapsulating the second die or die stack and at least one portion of the first molding compound. In this example, the first die or die stack is electrically coupled to the substrate using a first wire bond and the second die or die stack is electrically coupled to the substrate using a second wire bond. Additionally, the first molding compound encapsulates the first wire bond and the second molding compound encapsulates the second wire bond. Furthermore, a footprint of the second die overlaps a footprint of the first die.

公开(公告)号：US20200235018A1

公开(公告)日：2020-07-23

申请号：US16250683

申请日：2019-01-17

Applicant: Intel Corporation

Inventor： Hyoung Il KIM ,  Yi XU ,  Florence PON

IPC: H01L21/66 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00

Abstract: Embodiments described herein are directed to a temporary interconnect for use in testing one or more devices (e.g., one or more dies, inductors, capacitors, etc.) formed in semiconductor package. In one scenario, a temporary interconnect acts an electrical bridge that electrically couples a contact pad on a surface of a substrate and the test pad. Coupling the contact pad and the test pad to each other enables the device(s) coupled the contact pad to be tested. Following testing, the temporary interconnect can be removed or severed so that an electrical break is formed in the conductive path between test pad and the contact pad.

公开(公告)号：US20190273067A1

公开(公告)日：2019-09-05

申请号：US16349096

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Yi XU

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: Semiconductor packages including active die stacks, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package includes an active die having a top surface covered by a molding compound, and a bonding pad attached to only one interconnect wire. A method of fabricating the semiconductor package includes bridging a pair of dies stacks by the interconnect wire, and dividing the interconnect wire to form separate wire segments attached to respective die stacks.

公开(公告)号：US20200212009A1

公开(公告)日：2020-07-02

申请号：US16235859

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Yi XU ,  Hyoung Il KIM ,  Florence PON

IPC: H01L25/065 ,  H01L21/66

Abstract: Embodiments described herein provide techniques for testing a semiconductor package by using a diode to couple a test pad to a contact pad. In one scenario, a package comprises a die stack comprising one or more dies and a molding compound encapsulating the die stack. In this package, a substrate is over the molding compound. Also, a test pad and a contact pad are on a surface of the substrate. The contact pad is coupled to the die stack. A diode couples the test pad to the contact pad. In one example, the test pad is coupled to a P side of the diode's P-N junction and the contact pad is coupled to an N side of the diode's P-N junction. In operation, current can flow from the test pad through the contact pad (and the die stack), but current cannot flow from the contact pad through the test pad.