公开(公告)号：US20210057326A1

公开(公告)日：2021-02-25

申请号：US17053144

申请日：2018-12-12

Applicant: INTEL CORPORATION

Inventor： Zhicheng DING ,  Bin LIU ,  Yong SHE ,  Zhijun XU

IPC: H01L23/525 ,  H01L25/065 ,  H01L23/00

Abstract: Embodiments described herein provide techniques of forming an interconnect structure using lithographic and deposition processes. The interconnect structure can be used to couple components of a semiconductor package. For one example, a semiconductor package includes a die stack and an interconnect structure formed on the die stack. The die stack comprises a plurality of dies. Each die in the die stack comprises: a first surface; a second surface opposite the first surface; sidewall surfaces coupling the first surface to the second surface; and a pad on the first surface. A one sidewall surface of one of the dies has a sloped profile. The semiconductor package also includes an interconnect structure positioned on the first surfaces and the sidewall with the sloped profile. In this semiconductor package, the interconnect structure electrically couples the pad on each of the dies to each other.

公开(公告)号：US20180331004A1

公开(公告)日：2018-11-15

申请号：US15772483

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Mao GUO ,  John G. MEYERS ,  Yong SHE ,  Bin LIU ,  Lingyan L. TAN

IPC: H01L23/28 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/28 ,  H01L23/02 ,  H01L23/3128 ,  H01L23/5385 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A system in package and method of making as system in package are disclosed. The system in package has a substrate (102) with a plurality of passive devices (104) mounted thereon. A molding compound (106) envelopes the plurality of passive devices (104) to define a flat surface (116) substantially parallel to a surface of the substrate (102). A plurality of integrated circuit dies (110) is coupled successively to the flat surface (116).

公开(公告)号：US20220122907A1

公开(公告)日：2022-04-21

申请号：US17425227

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Xiaoying TANG ,  200241 DING ,  Bin LIU ,  Yong SHE ,  Zhijun XU

IPC: H01L23/498 ,  H01L23/00

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a package substrate with a top surface, a corner portion, and a plurality of solder balls on the top surface of the package substrate. The semiconductor package also includes a pattern on the corner portion of the package substrate. The pattern may have a width substantially equal to a width of the solder balls. The pattern may also include a continuous line having solder materials. The semiconductor package may include a plurality of conductive pads on the package substrate. The conductive pads may be coupled to the pattern. The pattern may have a z-height that is substantially equal to a z-height of the solder balls, and have one or more outer edges, where the outer edges of the pattern are sidewalls. The sidewalls of the pattern may be substantially vertical or tapered sidewalls.

公开(公告)号：US20220093568A1

公开(公告)日：2022-03-24

申请号：US17424839

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Jianfeng HU ,  Zhicheng DING ,  Yong SHE ,  Zhijun XU

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a package substrate with a plurality of cavities, and a plurality of adhesives in the cavities of the package substrate. The semiconductor package also includes a plurality of stacked dies over the adhesives and the package substrate, where the stacked dies are coupled to the adhesives with spacers. The spacers may be positioned below outer edges of the stacked dies. The adhesives may include a plurality of films. The semiconductor package may further include a plurality of interconnects coupled to the stacked dies and package substrate, a plurality of electrical components on the package substrate, a mold layer over the stacked dies, interconnects, spacers, adhesives, and electrical components, and a plurality of adhesive layers coupled to the plurality of stacked dies, where one of the adhesive layers couples the stacked dies to the spacers.

公开(公告)号：US20190103409A1

公开(公告)日：2019-04-04

申请号：US15721703

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Yi XU ,  Florence PON ,  Yong SHE

IPC: H01L27/112 ,  G06F17/50 ,  H01L21/768 ,  H01L23/525 ,  H03K19/177

CPC classification number: H01L27/1128 ,  G06F17/505 ,  G06F17/5068 ,  H01L21/768 ,  H01L23/5252 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/11206 ,  H01L2224/05554 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/8309 ,  H01L2224/83143 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/14 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1778 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012

Abstract: An IC package, comprising a substrate and two or more vertically stacked dies disposed within the substrate, wherein all the edges of the two or more dies are aligned with respect to one another, wherein at least two dies of the two or more vertically stacked dies are coupled directly to one another by at least one wire bonded to the ones of the at least two dies.

公开(公告)号：US20190051627A1

公开(公告)日：2019-02-14

申请号：US16078579

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Yong SHE

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/48 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/48 ,  H01L24/05 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48453 ,  H01L2224/48464 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Techniques and mechanisms for provide interconnection with integrated circuitry. In an embodiment, a packaged device includes a substrate and one or more integrated circuit (IC) dies. A first conductive pad is formed at a first side of a first IC die, and a second conductive pad is formed at a second side of the substrate or another IC die. Wire bonding couples a wire between the first conductive pad and the second conductive pad, wherein a distal end of the wire is bonded, via a bump, to an adjoining one of the first conductive pad and the second conductive pad. A harness of the bump, which is less than a hardness of the wire, mitigates damage to the adjoining pad that might otherwise occur as a result of wire bonding stresses. In another embodiment, the wire includes copper (Cu) and the bump includes gold (Au) or silver (Ag).

公开(公告)号：US20190019777A1

公开(公告)日：2019-01-17

申请号：US15749760

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Yong SHE ,  John G. MEYERS ,  Zhicheng DING ,  Richard PATTEN

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/49 ,  H01L23/00 ,  H01L23/50 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/488 ,  H01L23/49 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/33 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48249 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/83007 ,  H01L2224/92174 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/29099 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution Layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.