公开(公告)号：US11894344B2

公开(公告)日：2024-02-06

申请号：US17714979

申请日：2022-04-06

Applicant: INTEL CORPORATION

Inventor： Zhijun Xu ,  Bin Liu ,  Yong She ,  Zhicheng Ding

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

公开(公告)号：US20220230995A1

公开(公告)日：2022-07-21

申请号：US17714979

申请日：2022-04-06

Applicant: INTEL CORPORATION

Inventor： Zhijun Xu ,  Bin Liu ,  Yong She ,  Zhicheng Ding

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

公开(公告)号：US11302671B2

公开(公告)日：2022-04-12

申请号：US16641221

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Zhijun Xu ,  Bin Liu ,  Yong She ,  Zhicheng Ding

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

公开(公告)号：US12027496B2

公开(公告)日：2024-07-02

申请号：US17424839

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Jianfeng Hu ,  Zhicheng Ding ,  Yong She ,  Zhijun Xu

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/26152 ,  H01L2224/32145 ,  H01L2224/32237 ,  H01L2224/33181 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/73215 ,  H01L2224/73263 ,  H01L2924/35121

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a package substrate with a plurality of cavities, and a plurality of adhesives in the cavities of the package substrate. The semiconductor package also includes a plurality of stacked dies over the adhesives and the package substrate, where the stacked dies are coupled to the adhesives with spacers. The spacers may be positioned below outer edges of the stacked dies. The adhesives may include a plurality of films. The semiconductor package may further include a plurality of interconnects coupled to the stacked dies and package substrate, a plurality of electrical components on the package substrate, a mold layer over the stacked dies, interconnects, spacers, adhesives, and electrical components, and a plurality of adhesive layers coupled to the plurality of stacked dies, where one of the adhesive layers couples the stacked dies to the spacers.

公开(公告)号：US11990395B2

公开(公告)日：2024-05-21

申请号：US17425227

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Xiaoying Tang ,  Zhicheng Ding ,  Bin Liu ,  Yong She ,  Zhijun Xu

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/1319 ,  H01L2224/14179 ,  H01L2224/16227 ,  H01L2224/27849 ,  H01L2224/81815 ,  H01L2924/15311

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a package substrate with a top surface, a corner portion, and a plurality of solder balls on the top surface of the package substrate. The semiconductor package also includes a pattern on the corner portion of the package substrate. The pattern may have a width substantially equal to a width of the solder balls. The pattern may also include a continuous line having solder materials. The semiconductor package may include a plurality of conductive pads on the package substrate. The conductive pads may be coupled to the pattern. The pattern may have a z-height that is substantially equal to a z-height of the solder balls, and have one or more outer edges, where the outer edges of the pattern are sidewalls. The sidewalls of the pattern may be substantially vertical or tapered sidewalls.

公开(公告)号：US11742284B2

公开(公告)日：2023-08-29

申请号：US17053144

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Zhicheng Ding ,  Bin Liu ,  Yong She ,  Zhijun Xu

IPC: H01L23/525 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/525 ,  H01L24/48 ,  H01L25/0657 ,  H01L2924/15311

Abstract: Embodiments described herein provide techniques of forming an interconnect structure using lithographic and deposition processes. The interconnect structure can be used to couple components of a semiconductor package. For one example, a semiconductor package includes a die stack and an interconnect structure formed on the die stack. The die stack comprises a plurality of dies. Each die in the die stack comprises: a first surface; a second surface opposite the first surface; sidewall surfaces coupling the first surface to the second surface; and a pad on the first surface. A one sidewall surface of one of the dies has a sloped profile. The semiconductor package also includes an interconnect structure positioned on the first surfaces and the sidewall with the sloped profile. In this semiconductor package, the interconnect structure electrically couples the pad on each of the dies to each other.

公开(公告)号：US20200227387A1

公开(公告)日：2020-07-16

申请号：US16641221

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Zhijun Xu ,  Bin Liu ,  Yong She ,  Zhicheng Ding

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.