公开(公告)号：US20240055385A1

公开(公告)日：2024-02-15

申请号：US18315537

申请日：2023-05-11

Applicant: WISTRON NEWEB CORPORATION

Inventor： KUO-HUA HSIEH ,  CHAO-CHIEH CHAN ,  MING-JHE WU ,  CHIH-YANG WENG

IPC: H01L23/00 ,  H01L23/373

CPC classification number: H01L24/17 ,  H01L23/3737 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/10 ,  H01L24/26 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/73 ,  H01L2224/11318 ,  H01L2224/10175 ,  H01L2224/1319 ,  H01L2924/0665 ,  H01L2224/13021 ,  H01L2224/14132 ,  H01L2224/16237 ,  H01L2224/17519 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81862 ,  H01L2224/17517 ,  H01L2224/17051 ,  H01L2224/14152 ,  H01L2224/26175 ,  H01L2224/2731 ,  H01L2224/29021 ,  H01L2224/29013 ,  H01L2224/29012 ,  H01L2224/2919 ,  H01L2224/30155 ,  H01L2224/3015 ,  H01L2224/30051 ,  H01L2224/32237 ,  H01L2224/83007 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/73203

Abstract: A package structure and a method for fabricating the same are provided. The package structure includes a substrate, a semiconductor package and an adhesive body. The substrate has a first board surface and a second board surface. The semiconductor package has an upper surface and a lower surface, is disposed on the first board surface and electrically connected to the substrate through pins, and has a first vertical projection on the first board surface. An adhesive groove is disposed on the first board surface and is located in at least one portion of the first vertical projection and a periphery of the first vertical projection. The adhesive body is disposed in the adhesive groove, and protrudes to contact the lower surface, so as to fix the semiconductor package. The adhesive groove does not overlap with the pins, and the adhesive body does not contact the pins.

公开(公告)号：US20180261574A1

公开(公告)日：2018-09-13

申请号：US15694838

申请日：2017-09-03

Applicant: Toshiba Memory Corporation

Inventor： Yuji KARAKANE ,  Masatoshi FUKUDA ,  Soichi HOMMA ,  Masayuki MIURA ,  Naoyuki KOMUTA ,  Yuka AKAHANE ,  Yukifumi OYAMA

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/29 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/6836 ,  H01L21/76897 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/1415 ,  H01L2224/1416 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81065 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/1438 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device includes a wiring substrate having a first surface, a stacked body on the first surface, the stacked body comprising a first chip, a second chip having a through via and positioned between the first chip and the first surface, and a third chip, a first resin contacting the first surface and the third chip, and a second resin sealing the stacked body. The first and second resins are made of different materials.

公开(公告)号：US09997484B2

公开(公告)日：2018-06-12

申请号：US15252139

申请日：2016-08-30

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takeori Maeda ,  Masatoshi Fukuda ,  Ryoji Matsushima ,  Hideo Aoki

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/17 ,  H01L21/56 ,  H01L23/3142 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/1319 ,  H01L2224/1403 ,  H01L2224/14133 ,  H01L2224/14505 ,  H01L2224/14517 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/0635

Abstract: A semiconductor device includes a wiring substrate, a first semiconductor element, a second semiconductor element, a bump, a bonding portion, and a resin portion. The second semiconductor element is between the wiring substrate and the first semiconductor element. The bump is between the first and second semiconductor elements and electrically connects the first and second semiconductor elements. The bonding portion is between the first and second semiconductor elements, bonds the first semiconductor element to the second semiconductor element, and has a first elastic modulus. The resin portion has a second elastic modulus higher than the first elastic modulus. The resin portion is between the first and second semiconductor elements. The first semiconductor element is between a second portion of the resin portion and the wiring substrate. A third portion of the resin portion is overlapped with the first and second semiconductor elements.

公开(公告)号：US20180158790A1

公开(公告)日：2018-06-07

申请号：US15611804

申请日：2017-06-02

Applicant: TETOS Co., Ltd.

Inventor： Woo Young AHN ,  Seong Wan PARK

IPC: H01L23/00 ,  B23K35/02 ,  B23K35/26

CPC classification number: H01L24/13 ,  B23K35/0244 ,  B23K35/262 ,  H01L2224/1319 ,  H01L2224/13582 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2924/01322 ,  H01L2924/014

Abstract: Disclosed is a solder particle including a plastic core; a copper-free metal layer which is formed on an external surface of the plastic core; and a solder layer which is formed on the copper-free metal layer and contains not less than 85 wt % tin. Thus, it is possible to provide a solder particle with a copper-free metal layer, which is excellent in strength and conductivity and prevents or minimizes generation of a void during a reflow process or the like.

公开(公告)号：US09881900B2

公开(公告)日：2018-01-30

申请号：US15379437

申请日：2016-12-14

Applicant: ROHM CO., LTD.

Inventor： Hirofumi Takeda ,  Yoshihisa Takada

IPC: H01L23/24 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0652 ,  G01C17/30 ,  H01L23/13 ,  H01L23/147 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/11618 ,  H01L2224/11825 ,  H01L2224/11826 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13566 ,  H01L2224/13583 ,  H01L2224/13647 ,  H01L2224/13666 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/10158 ,  H01L2924/15156 ,  H01L2924/15157 ,  H01L2924/15321 ,  H01L2924/19102 ,  H01L2924/19105 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00012

Abstract: A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate (100D), which includes a main surface (101D) and a recess (108D) depressed from the main surface (101D), and includes a semiconductor material; a wiring layer (200D) in which at least a portion thereof is formed on the substrate (100D); one or more first elements (370D) accommodated in the recess (108D); a sealing resin (400D) covering at least a portion of the one or more first elements (370D) and filled in the recess (108D); and a plurality of columnar conductive portions (230D) penetrating through the sealing resin (400D) in the depth direction of the recess (108D), and respectively connected with the portion of the wiring layer (200D) that is formed at the recess (108D).

公开(公告)号：US20170365551A1

公开(公告)日：2017-12-21

申请号：US15691654

申请日：2017-08-30

Applicant: ams AG

Inventor： Cathal CASSIDY ,  Martin SCHREMS ,  Franz SCHRANK

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/532 ,  H01L23/552 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor substrate is provided with an annular cavity extending from a front side of the substrate to an opposite rear side. A metallization is applied in the annular cavity, thereby forming a through-substrate via and leaving an opening of the annular cavity at the front side. A solder ball is placed above the opening and a reflow of the solder ball is effected, thereby forming a void of the through-substrate via, the void being covered by the solder ball.

公开(公告)号：US09818712B2

公开(公告)日：2017-11-14

申请号：US14596888

申请日：2015-01-14

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Paige M. Holm ,  Vijay Sarihan

IPC: H01L23/02 ,  H01L23/00

CPC classification number: H01L24/17 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06134 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/1319 ,  H01L2224/14134 ,  H01L2224/14179 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/146 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2224/03 ,  H01L2224/11

Abstract: A device package includes a substrate having an active surface. Electrical connection bumps are deposited on the active surface and are arranged in an array having a perimeter. At least one electronic component is formed at a region of the active surface, where the region is located outside of the perimeter of the array of electrical connection bumps. When the device package is coupled with external circuitry via the electrical connection bumps, the region at which the electronic component is formed is suspended over the electronic circuitry. This region is subject to a lower stress profile than a region of the active surface circumscribed by the perimeter. Thus, stress sensitive electronic components can be located in this lower stress region of the active surface.

公开(公告)号：US09807888B2

公开(公告)日：2017-10-31

申请号：US14588321

申请日：2014-12-31

Applicant: TAI-SAW TECHNOLOGY CO., LTD.

Inventor： Yu-Tung Huang ,  Ming-Hung Chang

IPC: H01L23/02 ,  H05K3/30 ,  H01L23/498 ,  H05K1/11 ,  H01L23/00

CPC classification number: H05K3/305 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/1319 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/81385 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H05K1/111 ,  H05K2201/0373 ,  H05K2201/09781 ,  Y02P70/613 ,  Y10T156/10 ,  H01L2924/00014

Abstract: A conducting package structure includes a substrate and a conducting material. The conducting material is formed to a first patterned structure. The first patterned structure has a first surface which is connected to the substrate and a patterned second surface opposite to the first surface.

公开(公告)号：US20170263571A1

公开(公告)日：2017-09-14

申请号：US15453964

申请日：2017-03-09

Applicant: IBIDEN CO., LTD.

Inventor： Teruyuki ISHIHARA ,  Hiroyuki BAN ,  Kosuke IKEDA ,  Haiying MEI

IPC: H01L23/552 ,  H01L21/768 ,  H01L23/053 ,  H01L23/48

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/053 ,  H01L23/295 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16237 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An electronic component built-in substrate includes an insulating substrate having a through hole and an inner wall surrounding the through hole, an electronic component accommodated in the through hole of the substrate, a sealing member filling the through hole such that the sealing member is covering the electronic component in the through hole of the substrate and exposing a terminal of the electronic component on a first side of the substrate, and a shield layer structure including a first metal film and a second metal film formed such that the first metal film is formed on the inner wall of the substrate and surrounding the through hole of the substrate and that the second metal film is formed on a second side of the substrate on the opposite side with respect to the first side and covering an opening of the through hole on the second side of the substrate.

公开(公告)号：US09735101B2

公开(公告)日：2017-08-15

申请号：US15283183

申请日：2016-09-30

Applicant: ams AG

Inventor： Cathal Cassidy ,  Martin Schrems ,  Franz Schrank

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532 ,  H01L23/552 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises an annular cavity (18) and a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for three-dimensional integration is offered by this scheme.