公开(公告)号：US20240289286A1

公开(公告)日：2024-08-29

申请号：US18572199

申请日：2021-09-26

Applicant: Intel Corporation

Inventor： Zhonghua SUN ,  Changcheng LIU ,  Yi SUN ,  Cong ZHANG ,  Di ZHANG ,  Zhuangzhi LI

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1668 ,  G06F13/404

Abstract: Examples relate to a concept for providing access to remote memory. A network interface controller apparatus comprises circuitry configured to obtain a memory transaction request with respect to memory of a first host hosting the network interface controller apparatus from a second host. The circuitry is configured to translate the memory transaction request to a cache transaction request. The circuitry is configured to provide the cache transaction request to the first host. The circuitry is configured to obtain a response to the cache transaction request from the first host. The circuitry is configured to provide information on the response to the cache transaction request to the second host.

公开(公告)号：US20220019444A1

公开(公告)日：2022-01-20

申请号：US17449098

申请日：2021-09-28

Applicant: Intel Corporation

Inventor： Di ZHANG ,  Sarathy JAYAKUMAR ,  Vincent ZIMMER ,  Fei LI ,  Bo HE ,  Zhuangzhi LI ,  Zhi JIN ,  Lin CHEN ,  Guomin JIANG

IPC: G06F9/4401 ,  G06F1/24

Abstract: An electronic device is disclosed, including a first set of processor cores including at least one processor core and a second set of processor cores including at least one processor core. The electronic device is configured such that during initialization of the electronic device: the first set of processor cores executes first initialization instructions in a first execution environment, the second set of processor cores executes second initialization instructions in a second execution environment, and the first set and the second set at least one of read or write to a shared register.